NDLI: The design and verification of packet processing engine model using SystemC

Content Provider	IEEE Xplore Digital Library
Author	Pei-Jun Ma Qing-He Zhao Yong Fan Meng Liu Kang Li
Copyright Year	2011
Description	Author affiliation: Dept. Microelectronics Xidian University, Xi'an, China (Pei-Jun Ma; Qing-He Zhao; Yong Fan; Meng Liu; Kang Li)
Abstract	The traditional hardware description languages (VHDL and Verilog) is not suitable for system-level modeling and Hardware Software Codesign, while the SystemC language is more suitable than the traditional HDL language for system-level modeling. This paper describes the packet processing engine(PPE) characteristics of XDNP network processor, analyze the advantage of system-level modeling in SystemC language, and use the SystemC language for the system-level modeling of the packet processing engine. In addition an independent simulation model is built, and the performance of packet processing engine is analyzed and verificated. Compared with the traditional hardware description language model we can obtain about 1.5 times simulation speed as much as that of HDL model.
Starting Page	1099
Ending Page	1101
File Size	204576
Page Count	3
File Format	PDF
ISBN	9781457703201
e-ISBN	9781457703218
DOI	10.1109/ICECC.2011.6066395
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-09
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Object oriented modeling Instruction sets SoC Hardware Registers System-on-a-chip Engines Packet Processing Engine SystemC
Content Type	Text
Resource Type	Article

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