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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Changlei Dongye |
| Copyright Year | 2011 |
| Description | Author affiliation: College of Information Science and Technology, Shandong University of Science and Technology, Qingdao, China (Changlei Dongye) |
| Abstract | FPGA and ASIC design based on SoC technology have been widely used in the embedded systems. A flexible interconnection scheme is crucial in SoC design. In this paper, we adopt the Wishbone bus to interconnect a variety of devices due to its open architecture and many a free IP core with a Wishbone interface supplied by OpenCores organization. In general SoC system, a single bus interconnects all devices that are not divided into high-performance unit such as CPU, on-chip ram and low-speed devices like uart, gpio and so on. It leads to a big problem: all Wishbone bus cycles run at the speed of the slowest device. We have to add the corresponding logic to regulate the system frequency for some low-speed devices, but it causes a new problem which increases the overall system power consumption. In view of the drawback, based on Wishbone bus, the paper proposes a double bus that makes first level Wishbone bus and the second level bus to interconnect the different devices according to the speed of the devices. Finally, we set up a SoC system to verify the performance of the proposed bus and the result shows that the double bus is feasible in low-power SoC design. |
| Starting Page | 3653 |
| Ending Page | 3656 |
| File Size | 484658 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457703201 |
| e-ISBN | 9781457703218 |
| DOI | 10.1109/ICECC.2011.6067598 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-09-09 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Bridges Power demand Wishbone IP core Double bus Integrated circuit interconnections SoC Switches Hardware System-on-a-chip IP networks |
| Content Type | Text |
| Resource Type | Article |
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