NDLI: High performance and power efficient 32-bit carry select adder using hybrid PTL/CMOS logic style

Content Provider	IEEE Xplore Digital Library
Author	Suri, L. Lamba, D. Kritarth, K. Sharma, G.
Copyright Year	2013
Description	Author affiliation: Maharaja Surajmal Inst. of Technol., New Delhi, India (Suri, L.; Lamba, D.; Kritarth, K.; Sharma, G.)
Abstract	Highly-increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using Hybrid PTL/CMOS logic style. This work evaluates and analyses the performance of the proposed designs in terms of area, delay, power, and their products in 90nm CMOS process technology. The results analysis is showing that the proposed CSA structure shows better result in terms of area, power and PDP (Power Delay Product) than the others.
Sponsorship	IEEE Kerala Sect.
Starting Page	765
Ending Page	768
File Size	261808
Page Count	4
File Format	PDF
ISBN	9781467350891
e-ISBN	9781467350907
DOI	10.1109/iMac4s.2013.6526509
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-22
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Hybrid PTL/CMOS Logic gates Hybrid power systems CMOS integrated circuits Delays Power dissipation PDP Adders
Content Type	Text
Resource Type	Article

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