NDLI: Novel high speed vedic mathematics multiplier using compressors

Content Provider	IEEE Xplore Digital Library
Author	Huddar, S.R. Rupanagudi, S.R. Kalpana, M. Mohan, S.
Copyright Year	2013
Description	Author affiliation: Dept. of ECE, RYMEC, Bellary, India (Kalpana, M.) \|\| Dept. of Telecom, Atria Inst. of Technol., Bangalore, India (Mohan, S.) \|\| WorldServe Educ., Bangalore, India (Huddar, S.R.; Rupanagudi, S.R.)
Abstract	With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
Sponsorship	IEEE Kerala Sect.
Starting Page	465
Ending Page	469
File Size	457029
Page Count	5
File Format	PDF
ISBN	9781467350891
e-ISBN	9781467350907
DOI	10.1109/iMac4s.2013.6526456
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-22
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Vedic Mathematics Very large scale integration 4:2 Compressor Compressors Mathematics High speed multiplier Modified Booth's multiplier Booth's multiplier Computer architecture 7:2 Compressor Urdhwa Tiryakbhyam Sutra Adders Field programmable gate arrays Propagation delay
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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