NDLI: Process integration for backside illuminated image sensor stacked with Analog-to-Digital Conversion chip

Content Provider	IEEE Xplore Digital Library
Author	Chang, H.H. Chien, C.H. Lee, Y.C. Lee, S.M. Wang, J.C. Huang, Y.W. Zhan, C.J. Hsiao, Z.C. Tzeng, P.J. Lee, C.H. Chen, T.S. Ko, C.T. Lo, W.C. Kao, M.J.
Copyright Year	2014
Description	Author affiliation: Ind. Technol. Res. Inst., Hsinchu, Taiwan (Chang, H.H.; Chien, C.H.; Lee, Y.C.; Lee, S.M.; Wang, J.C.; Huang, Y.W.; Zhan, C.J.; Hsiao, Z.C.; Tzeng, P.J.; Lee, C.H.; Chen, T.S.; Ko, C.T.; Lo, W.C.; Kao, M.J.)
Abstract	In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500 μm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 μm after thinning and the total thickness variation is around 1 μm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.
Sponsorship	Japan Coun. CPMT Chapt.
Starting Page	39
Ending Page	43
File Size	1593769
Page Count	5
File Format	PDF
e-ISBN	9784904090114
DOI	10.1109/ICEP.2014.6826657
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JIEP
Subject Keyword	Chip on Chip Three-dimensional displays Wafer Level Packaging Interconnections for 3D Integration Materials CMOS image sensors Tin Chip-Package Interaction Etching Bonding Temporary Bonding/De-Bonding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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