NDLI: Equalizer design and performance trade-offs in ADC-based serial links

Content Provider	IEEE Xplore Digital Library
Author	Jaeha Kim Jihong Ren Leibowitz, B.S. Satarzadeh, P. Abbasfar, A.-A. Zerbe, J.
Copyright Year	2010
Description	Author affiliation: Rambus, Inc., Los Altos, CA, U.S.A. (Jaeha Kim; Jihong Ren; Leibowitz, B.S.; Satarzadeh, P.; Abbasfar, A.-A.; Zerbe, J.)
Abstract	To address the increasing demand but potential power/area penalties of implementing ADC-based high-speed serial receivers, this paper analyzes the performance benefit of using non-uniform quantization and describes a way of determining the optimal set of ADC quantization thresholds. In contrast to common wisdom, the ADC thresholds for the minimum bit-error rate (BER) can be very different from those for the minimum quantization errors, especially with limited ADC resolution. It is recognized that the loop-unrolling DFE receiver and ADC-based DFE receiver are functionally equivalent and thus can share some design principles. The proposed reduced-slicer partial-response DFE (RS-PRDFE) receiver leverages this fact and achieves the BER of a 3∼4-bit uniform ADC only with 4 data slicers. However, performing linear equalization (LE) in digital domain in addition to the DFE may incur severe performance penalty if the ADC resolution is kept coarse. Therefore, for practical implementations, it is more reasonable to realize the LE in analog domain. Analyses based on the measured results with 3″ and 10.6″ backplane channels support this claim.
Starting Page	1
Ending Page	8
File Size	798664
Page Count	8
File Format	PDF
ISBN	9781424457588
ISSN	21523630
e-ISBN	9781424457601
DOI	10.1109/CICC.2010.5617601
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Receivers Decision feedback equalizers Bit error rate Quantization Transceivers Backplanes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

BER-based adaptive ADC-equalizer based receiver for communication links

Equalizer complexity/performance trade-offs for high data-rate IR-UWB linear receivers in multipath channels

A novel equalizer for the high-loss backplane at Nyquist frequency

Embedded equalization for ADC-based serial I/O receivers

Optimal design for decision-feedback equalizer

Statistical modeling of metastability in ADC-based serial I/O receivers

A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers

A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS

Equalizer design and performance trade-offs in ADC-based serial links

Similar Documents

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

BER-based adaptive ADC-equalizer based receiver for communication links

Equalizer complexity/performance trade-offs for high data-rate IR-UWB linear receivers in multipath channels

A novel equalizer for the high-loss backplane at Nyquist frequency

Embedded equalization for ADC-based serial I/O receivers

Optimal design for decision-feedback equalizer

Statistical modeling of metastability in ADC-based serial I/O receivers

A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers

A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS

Equalizer design and performance trade-offs in ADC-based serial links