NDLI: Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Duarte, D. Hsu, S. Wong, K. Huang, M. Taylor, G.
Copyright Year	2010
Description	Author affiliation: Logic Technology Development, Intel Corporation, Hillsboro, OR 97124, USA (Duarte, D.; Huang, M.; Taylor, G.) \|\| Anax Corporation, Beaverton, OR USA (Wong, K.) \|\| Qualcomm, San Diego, CA USA (Hsu, S.)
Abstract	A novel self-biased PLL design incorporating a low-gain interpolated inverter-based ring oscillator VCO accomplishes several improvements for general purpose clock generation, namely lower bandwidth and lower short and medium-term accumulation jitter due to thermal noise and reference clock noise, while not sacrificing PSRR, area, and PVT insensitivity. Charge pump programmability provides an effective mechanism for bandwidth adjustments without requiring large circuit duplicates. Data collected on a high-k, metal gate 45 nm process confirms the suitability of the proposed scheme.
Starting Page	1
Ending Page	4
File Size	159329
Page Count	4
File Format	PDF
ISBN	9781424457588
ISSN	21523630
e-ISBN	9781424457601
DOI	10.1109/CICC.2010.5617473
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage-controlled oscillators Jitter Phase locked loops Charge pumps Clocks Damping Voltage control
Content Type	Text
Resource Type	Article

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Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS