NDLI: A 9.15mW $0.22mm^{2}$ 10b 204MS/s pipelined SAR ADC in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Young-Deuk Jeon Young-Kyun Cho Jae-Won Nam Kwi-Dong Kim Woo-Yol Lee Kuk-Tae Hong Jong-Kee Kwon
Copyright Year	2010
Description	Author affiliation: LG Electronics, Korea (Woo-Yol Lee; Kuk-Tae Hong) \|\| Electronics and Telecommunications Research Institute, Korea (Young-Deuk Jeon; Young-Kyun Cho; Jae-Won Nam; Kwi-Dong Kim; Jong-Kee Kwon)
Abstract	This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies $0.22mm^{2}$ and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step.
Starting Page	1
Ending Page	4
File Size	459866
Page Count	4
File Format	PDF
ISBN	9781424457588
ISSN	21523630
e-ISBN	9781424457601
DOI	10.1109/CICC.2010.5617457
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Clocks CMOS integrated circuits Timing Generators Capacitance Frequency measurement
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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