NDLI: Characterization, simulation, and modeling of FET source/drain diffusion resistance

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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2008 IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 2008 custom integrated circuits conference

Session quick index

Table of contents

More than Moore

Session 2 - Statistical modeling

Process variability at the 65nm node and beyond

Mismatch analysis and statistical design at 65 nm and below

Statistical prediction of circuit aging under process variations

Session 3 - Power management

A fully-integrated 0.18μm CMOS DC-DC step-down converter, using a bondwire spiral inductor

A 90–240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking

Fast transient technique (FTT) in buck current-mode DC-DC converters for low-voltage SoC systems

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design

Built-in resistance compensation (BRC) technique for fast charging Li-Ion battery charger

Session 4 - High-speed test, characterization, and debug

A voltage drop aware crosstalk measurement with multi-aggressors in 65nm process

Measurements of the silicon die characteristics of packaged drivers for high-speed I/O

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications

Non-destructive IC defect localization using optical beam-based imaging

Session 5 - Broadband circuit techniques for emerging wireless communications

Emerging application opportunities for SiGe technology

A 0.8GHz–10.6GHz SDR low-noise amplifier in 0.13-μm CMOS

A 1.3–6 GHz triple-mode CMOS VCO using coupled inductors

Session 6 - Advanced SoC/SiP integration & co-design

A SOC/SOP co-design approach for mmW CMOS in QFN technology

Chip to carrier C4 technology challenges with Pb free solders

A study on process-compatibility in CMOS-first MEMS-last integration

Session 7 - High resolution converters

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and −98 dB THD

A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers

74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain

A/D converter trends: Power dissipation, scaling and digitally assisted architectures

A 16b 10MS/s digitally self-calibrated ADC with time constant control

A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers

Session 8 - Characterization and test methods for device variability in nanoscale technologies

An array-based test circuit for fully automated gate dielectric breakdown characterization

A high sensitivity process variation sensor utilizing sub-threshold operation

Measurement and analysis of variability in 45nm strained-Si CMOS technology

Within-die gate delay variability measurement using re-configurable ring oscillator

Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI’s

Session 9 - Broadband circuit techniques for emerging wireless communications

MIMO techniques for high data rate radio communications

Wireless interconnection within a hybrid engine controller board

Session 10 - Panel discussion Sure, Moore’s Law can continue, but should it:

Monday poster session

A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS

A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration

Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz

A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling

A continuous-time input pipeline ADC

A 0.8 V asynchronous ADC for energy constrained sensing applications

Modeling, design and optimization of hybrid electromagnetic and piezoelectric MEMS energy scavengers

Amorphous silicon logic circuits on flexible substrates

Frequency tunable silicon carbide resonators for MEMS above IC

MEMS wafer-level vacuum packaging with transverse interconnects for CMOS integration

Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement

Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application

A high-speed, low-power 3D-SRAM architecture

Early prediction of product performance and yield via technology benchmark

A FPGA vernier digital-to-time converter with 3.56ps resolution and −0.23∼+0.2LSB inaccuracy

RASP 2.8: A new generation of floating-gate based field programmable analog array

Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz

A general weak nonlinearity model for LNAs

Modeling and synthesis of wide-band switched-resonators for VCOs

Faster statistical cell characterization using adjoint sensitivity analysis

An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process

A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer

A scalable digitalized buffer for gigabit I/O

Broadband transimpedance amplifier in 0.35-μm SiGe BiCMOS technology for 10-Gb/s optical receiver analog front-end application

A multifunction transceiver RFIC for 802.11a/b/g WLAN and DVB-H applications

A fully integrated zero-IF mobile TV tuner RFIC for S-band CMMB application

Session 11 - Compact modeling

Compact modeling of multiple-gate MOSFETs

Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges

Modeling ionizing radiation effects in solid state materials and CMOS devices

Characterization, simulation, and modeling of FET source/drain diffusion resistance

Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits

Session 12 - High speed A/D converters

Time-interleaved analog-to-digital converters

A 12b 50MSPS 34mW pipelined ADC

Background ADC calibration in digital domain

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS

A 24GS/s 5-b ADC with closed-loop THA in 0.18μm SiGe BiCMOS

Session 13 - Biomedical, sensors and MEMS

A biomedical implantable FES battery-powered micro-stimulator

CMOS LSI-based multi-chip flexible retinal prosthesis device for subretinal implantation

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation

A micro-power neural spike detector and feature extractor in .13μm CMOS

A compact and programmable high-frequency oscillator based on a MEMS resonator

Session 14 - Advanced SoCs - techniques and applications

Characterization and design for variability and reliability

A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines

A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision

A low-power IC design for the wireless monitoring system of the orthopedic implants

Tessellation-enabled shader for a bandwidth-limited 3D graphics engine

Session 15 - IC Technology - more Moore and more than Moore

Lithography options for the 32nm half pitch node and beyond

45nm high-k + metal gate strain-enhanced CMOS transistors

Will BiCMOS stay competitive for mmW applications ?

Microelectronics for the real world: “Moore” versus “More than Moore”

Session 16 - Embedded memory

A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne

A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode

Compensation of systematic variations through optimal biasing of SRAM wordlines

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology

Robust ultra-low voltage ROM design

A million cycle 0.13um 1Mb embedded SONOS Flash memory using Successive Approximated Read Calibration

Session 17 - Clocking circuits

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI

Clocking circuits for a 16Gb/s memory interface

A 1V 15.6mW 1–2GHz −119dBc/Hz @ 200kHz clock multiplying DLL

A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of −28dB

20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS

A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation

A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation

A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction

Session 18 - Millimeter-wave circuit techniques

Millimeter-wave CMOS integrated circuits for gigabit WPAN applications

A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links

Low-cost fully integrated BiCMOS transceiver for pulsed 24-GHz automotive radar sensors

A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communications

A low power 20 GHz 1.5 Gb/s CMOS injection-pulling FSK modulator and frequency discriminator for 60GHz links

A 24/77GHz dual-band BiCMOS frequency synthesizer

An X/Ku-band frequency synthesizer using a 9-Bit quadrature DDS

Tuesday poster session

A dynamic offset control technique for comparator design in scaled CMOS technology

A low-voltage OP amp with digitally controlled algorithmic approximation

A 105.5 dB, 0.49 $mm^{2}$ Audio ΣΔ modulator using chopper stabilization and fully randomized DWA

An ultra low power 1V, 220nW temperature sensor for passive wireless applications

A 9-Bit configurable current source with enhanced output resistance for cochlear stimulators

Super-resolution: Imaging beyond the pixel size limit

Polysilicon vertical actuator powered with waste heat

Low noise μWatt interface circuits for wireless implantable real-time digital blood pressure monitoring

A flexible decoder IC for WiMAX QC-LDPC codes

Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage

The Superchip: Innovative teaching of IC design and manufacture

A 3D graphics processor with fast 4D vector inner product units and power aware texture cache

Timing yield enhancement through soft edge flip-flop based design

1/5 power reduction by global optimization based on fine-grained body biasing

A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor

Active autonomous AC-DC converter for Piezoelectric Energy Scavenging Systems

A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR

A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13μm CMOS

Active deskew in injection-locked clocking

A 53 GHz DCO for mm-wave WPAN

Twisted inductors for low coupling mixed-signal and RF applications

A common-base linear rf power amplifier for 3G cellular applications

Design of low power CMOS ultra-wideband 3.1–10.6 GHz pulse-based transmitters

Session 19 - Low power and non-traditional RF tranceivers

Energy-efficient wireless front-end concepts for ultra lower power radio

A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver

A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks

A 3.5-mW 15-Mbps O-QPSK transmitter for real-time wireless medical imaging applications

A CMOS direct conversion transmitter with integrated in-band harmonic suppression for IEEE 802.22 cognitive radio applications

A 5-GHz wireless LAN transmitter with integrated tunable high-Q RF filter

Session 20 - Advanced wireline techniques

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing

Phase-locking in wireline systems: Present and future

A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS

Wideband mmWave CML static divider in 65nm SOI CMOS technology

A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme

EMI resisting smart-power integrated LIN driver with reduced slope pumping

Session 21 - Leveraging the third Dimension

Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bump

Clock distribution networks for 3-D ictegrated Circuits

Inter-die signaling in three dimensional integrated circuits

Variability in 3-D integrated circuits

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation

SiP for GSM/EDGE in CMOS technology

Heterogeneous multicore SoC for secure multimedia applications

A 159.2mW SoC implementation of T-DMB receiver including stacked memories

Session 22 - Noise and oscillator simulation

Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs

A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessor

Characterization of random decision errors in clocked comparators

Noise tolerant oscillator design using perturbation projection vector analysis

Strong injection locking of low-Q LC oscillators

Session 23 - Analog techniques

A low power 1.3GHz dual-path current mode Gm-C filter

A 1V downconversion filter using duty-cycle controlled bandwidth tuning

A reconfigurable FIR filter embedded in a 9b successive approximation ADC

Voltage references for ultra-low supply voltages

Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process

Deep submicron effects on data converter building blocks

Session 24 - Advanced subsystems for connectivity and cellular radio

A highly linear SAW-less CMOS receiver using a mixer with embedded Tx filtering for CDMA

High-power digital envelope modulator for a polar transmitter in 65nm CMOS

A 2.4GHz, 20dBm class-D PA with single-bit digital polar modulation in 90nm CMOS

Linearity and efficiency enhancement strategies for 4G wireless power amplifier designs

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability

A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications

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Characterization, simulation, and modeling of FET source/drain diffusion resistance

Content Provider	IEEE Xplore Digital Library
Author	Ning Lu Dewey, B.
Copyright Year	2008
Description	Author affiliation: IBM Electron. Design Autom., Fishkill, NY (Dewey, B.) \|\| Semicond. R&D Center, IBM, Essex Junction, VT (Ning Lu)
Abstract	We present an innovative and comprehensive approach to characterize and model FET source/drain diffusion resistance. We present a set of new SPICE models for the parasitic resistance in FET source and drain regions. Our FET source/drain diffusion resistance model has been verified with field solver simulation results, and is found to be very accurate over a wide range of parameter values. We also present a set of micro testing structures to measure and characterize diffusion resistance. This approach has been validated using hardware data from a 65 nm SOI technology.
Starting Page	281
Ending Page	284
File Size	477726
Page Count	4
File Format	PDF
ISBN	9781424420186
DOI	10.1109/CICC.2008.4672076
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FETs Electric resistance Electrical resistance measurement Semiconductor device modeling Current Silicides SPICE Hardware Silicon USA Councils
Content Type	Text
Resource Type	Article

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