NDLI: Chip to carrier C4 technology challenges with Pb free solders

Content Provider	IEEE Xplore Digital Library
Author	Perfecto, E.D. Sundlof, B. Srivastava, K. Lu, M.
Copyright Year	2008
Description	Author affiliation: Syst. & Technol. Group, IBM, Hopewell Junction, NY (Perfecto, E.D.; Sundlof, B.; Srivastava, K.)
Abstract	IBMpsilas C4 interconnection technology has continuously evolved over a period of forty years, i.e. from evaporation, to electroplating to C4NP, a C4 New Process. IBMpsilas initial C4NP efforts are focused on Sn-based Pb-free solder technology, in line with client requirements. Currently, all IBM bumped lead-free C4s are produced using the C4NP technology. Sn-based lead-free solders pose unique challenges because of higher microhardness and anisotropy of the tin crystalline structure, as compared to Pb-based solders. The simultaneous design requirements of increased power and current density, increased I/O counts and larger chips, and weak BEOL structure with low-k or ultra-low-k dielectric, demand a careful material interaction optimization between under bump metallurgy (UBM), bump solder, laminate solder, and laminate surface finish. In this paper, we will be discussing the challenges and some solutions of lead-free C4 bumping in terms of mechanical and thermo-electromigration.
Starting Page	81
Ending Page	84
File Size	1312507
Page Count	4
File Format	PDF
ISBN	9781424420186
DOI	10.1109/CICC.2008.4672025
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Environmentally friendly manufacturing techniques Lead Laminates Anisotropic magnetoresistance Tin Crystallization Current density Crystalline materials Dielectric materials Inorganic materials
Content Type	Text
Resource Type	Article

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