NDLI: Test structures to quantify contact placement-impacted drain current variations

Content Provider	IEEE Xplore Digital Library
Author	Topaloglu, R.O. Zhi-Yuan Wu Icel, A.B.
Copyright Year	2010
Description	Author affiliation: GLOBALFOUNDRIES, Sunnyvale, CA, USA (Topaloglu, R.O.; Zhi-Yuan Wu; Icel, A.B.)
Abstract	The difference in the number of contacts across different transistors and standard cells results in current variations across the channel. In this work, we present test structures to target this effect and characterize and quantify the impact on 45 nm SOI silicon. After comparing the impact of contact resistance between 65 nm and 45 nm silicon, we provide and analyze our 45 nm test structure results and provide a means to extract mean contact resistance from our test structures. We observe that impact due to contact resistance can be up to 10% for 45 nm, while it could have been of less importance (less than 4%) for 65 nm technology. Such test structures and methodology help us provide intrinsic device models in 45 nm without inaccuracies or resistive double counting that may be introduced due to placement-impacted contact resistance variations.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	188
Ending Page	191
File Size	208087
Page Count	4
File Format	PDF
ISBN	9781424469123
e-ISBN	9781424469154
e-ISBN	9781424469147
DOI	10.1109/ICMTS.2010.5466822
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-22
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Contact resistance Silicon MOSFET circuits Routing Copper Electrical resistance measurement Semiconductor device modeling Microelectronics USA Councils
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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