NDLI: Robust ultra-low voltage ROM design

Content Provider	IEEE Xplore Digital Library
Author	Mingoo Seok Hanson, S. Jae-Sun Seo Sylvester, D. Blaauw, D.
Copyright Year	2008
Description	Author affiliation: Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI (Mingoo Seok; Hanson, S.; Jae-Sun Seo; Sylvester, D.; Blaauw, D.)
Abstract	SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18 mum CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100 mV over a conventional dynamic NAND ROM.
Starting Page	423
Ending Page	426
File Size	521699
Page Count	4
File Format	PDF
ISBN	9781424420186
DOI	10.1109/CICC.2008.4672110
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness Voltage Read only memory Circuit topology Circuit testing CMOS technology Random access memory Energy consumption Emergency power supplies Logic gates
Content Type	Text
Resource Type	Article

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