NDLI: Inter-die signaling in three dimensional integrated circuits

Content Provider	IEEE Xplore Digital Library
Author	Mineo, C. Jenkal, R. Melamed, S. Davis, W.R.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC (Mineo, C.; Jenkal, R.; Melamed, S.; Davis, W.R.)
Abstract	This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 $mm^{2}$ per tier was designed and tested. It is the first of its kind to demonstrate successful inter-tier signaling in a complex three dimensional design, and validates the technology as a viable alternative to the continued scaling of conventional CMOS processes. Simulated results show that when implemented in this 3D process, simple 3D mesh interconnection networks allow for the sharing of global routing resources for complex systems while consuming an extremely low 2 mW of power per transaction. Using these results, we establish the need for a 3D network simulator to quantify the advantage 3D circuit implementations have over 2D.
Starting Page	655
Ending Page	658
File Size	326153
Page Count	4
File Format	PDF
ISBN	9781424420186
DOI	10.1109/CICC.2008.4672171
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip Laboratories Circuit testing Signal processing Signal design CMOS technology CMOS process Multiprocessor interconnection networks Routing Circuit simulation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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