NDLI: A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer

Content Provider	IEEE Xplore Digital Library
Author	Jongshin Shin Jaehyun Park Bongjin Kim Jongjae Ryu Chiwon Kim JiYoung Kim Seung-Hee Yang Hyungoo Kim Jaewhui Kim
Copyright Year	2008
Description	Author affiliation: Syst. LSI, Samsung Electron., Giheung (Jongshin Shin; Jaehyun Park; Bongjin Kim; Jongjae Ryu; Chiwon Kim; JiYoung Kim; Seung-Hee Yang; Hyungoo Kim; Jaewhui Kim)
Abstract	A 65 nm HDMI TX PHY was designed with supply-regulated dual-tuning PLL and blending multiplexer. The proposed PLL uses a new dual-tuning scheme for small capacitor and low-jitter while keeping the supply regulation capability. A fractional-N operation for non-integer pixel clock generation was implemented with a blending multiplexer which enables seamless switching of high-speed multiphase clock. The fabricated PHY gives maximum 3.4 Gbps data rate per channel and shows 34 ps peak-to-peak data jitter.
Starting Page	237
Ending Page	240
File Size	948131
Page Count	4
File Format	PDF
ISBN	9781424420186
DOI	10.1109/CICC.2008.4672067
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Physical layer Phase locked loops Multiplexing Clocks Voltage-controlled oscillators Jitter Voltage control Circuits Large scale integration Capacitors
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer