NDLI: An Analytical Placer for VLSI Standard Cell Placement

Content Provider	IEEE Xplore Digital Library
Author	Jianli Chen Wenxing Zhu
Copyright Year	1982
Abstract	Placement is the process of determining the exact locations of circuit elements within a chip. It is a crucial step in very large scale integration (VLSI) physical design, because it affects routability, performance, and power consumption of a design. In this paper, we develop a new analytical placer to solve the VLSI standard cell placement problem. The placer consists of two phases, multilevel global placement (GP) and detailed cell placement (DP). In the stage of GP, during the clustering stage, we use a nonlinear programming technique and a best-choice clustering algorithm to take a global view of the whole netlist and placement information, and then use an iterative local refinement technique during the declustering stage to further distribute the cells and reduce the wirelength. In the stage of DP, we develop a fast legalization algorithm to make the solution by global placement legal and use a cell order polishing to improve the legal solution. The proposed algorithm is tested on the IBM standard cell benchmark circuits and Peko suites. Experimental results show that our placer obtains high-quality results in a reasonable running time.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1208
Ending Page	1221
Page Count	14
File Size	7692531
File Format	PDF
ISSN	02780070
Volume Number	31
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Standards Programming Very large scale integration Algorithm design and analysis Clustering algorithms Law very large scale integration (VLSI) physical design Analytical approach detailed placement global placement standard cell placement
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A fast hierarchical quadratic placement algorithm

Nonsmooth Optimization Method for VLSI Global Placement

Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement

SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement

Cell Merge: A basic-pre-clustering clustering algorithm for placement

LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs

Implementation and extensibility of an analytic placer

GORDIAN: VLSI placement by quadratic programming and slicing optimization

Legalizing a placement with minimum total movement

An Analytical Placer for VLSI Standard Cell Placement

Similar Documents

A fast hierarchical quadratic placement algorithm

Nonsmooth Optimization Method for VLSI Global Placement

Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement

SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement

Cell Merge: A basic-pre-clustering clustering algorithm for placement

LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs

Implementation and extensibility of an analytic placer

GORDIAN: VLSI placement by quadratic programming and slicing optimization

Legalizing a placement with minimum total movement

An Analytical Placer for VLSI Standard Cell Placement