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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tuo Li Shafique, M. Rehman, S. Ambrose, J.A. Henkel, J. Parameswaran, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia (Tuo Li; Ambrose, J.A.; Parameswaran, S.) || Dept. of Embedded Syst., Karlsruhe Inst. of Technol., Karlsruhe, Germany (Shafique, M.; Rehman, S.; Henkel, J.) |
| Abstract | Soft error has become a major adverse effect in CMOS based electronic systems. Mitigating soft error requires enhancing the underlying system with error recovery functionality, which typically leads to considerable design cost overhead, in terms of performance, power and area. For embedded systems, where stringent design constraints apply, such cost must be properly bounded. In this paper, we propose a HW/SW methodology DHASER, which enables efficient error recovery functionality for embedded ASIP-based multi-core systems. DHASER consists of three main parts: task level correctness (TLC) analysis, TLC-based processor/core customization, and runtime reliability-aware task management mechanism. It enables each individual ASIP-based processing core to dynamically adapt its specific error recovery functionality according to the corresponding task's characteristics (i.e., soft error vulnerability and execution time deadline). The goal is to optimize the overall system reliability while considering performance/throughput. The experimental results have shown that DHASER can significantly improve the reliability of the system, with little cost overhead, in comparison to the state-of-art counterparts. |
| Sponsorship | IEEE Counc. Electron. Design Autom. |
| Starting Page | 646 |
| Ending Page | 653 |
| File Size | 788892 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781479910717 |
| ISSN | 10923152 |
| DOI | 10.1109/ICCAD.2013.6691184 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-11-18 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Runtime Multicore processing Redundancy Adaptation models Optimization |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Software |
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