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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.90CH2924-9)

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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

A clock net reassignment algorithm using Voronoi diagram

Content Provider	IEEE Xplore Digital Library
Author	Edahiro, M.
Copyright Year	1990
Description	Author affiliation: NEC Corp., Kawasaki, Japan (Edahiro, M.)
Abstract	A novel algorithm is presented for the clock net reassignment problem in semi-custom layout design. The clock net reassignment is used to shorten clock nets by reconnecting clock drivers and flip-flops so as to obtain high performance LSIs. The proposed algorithm, by using the Voronoi diagram in computational geometry, is quite efficient and gives better assignments than existing techniques. The experimental results show that the algorithm yields a 10% reduction in net lengths in comparison with existing algorithms. The algorithm takes only 18 s to find an assignment for 167 drivers and 833 flip-flops.<>
Starting Page	420
Ending Page	423
File Size	318466
Page Count	4
File Format	PDF
ISBN	0818620552
DOI	10.1109/ICCAD.1990.129942
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-11-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Flip-flops Joining processes Steiner trees Heuristic algorithms Bipartite graph National electric code Algorithm design and analysis Computational geometry NP-hard problem
Content Type	Text
Resource Type	Article

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