NDLI: Floorplanning with pin assignment

Content Provider	IEEE Xplore Digital Library
Author	Pedram, M. Marek-Sadowska, M. Kuh, E.S.
Copyright Year	1990
Description	Author affiliation: Electron. Res. Lab., California Univ., Berkeley, CA, USA (Pedram, M.; Marek-Sadowska, M.; Kuh, E.S.)
Abstract	A hierarchical technique is presented for floorplanning and pin assignment of general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the external I/O pads and upper bound delay constraints for a set of critical nets, the authors determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for a Xerox general cell benchmark are reported.<>
Starting Page	98
Ending Page	101
File Size	445985
Page Count	4
File Format	PDF
ISBN	0818620552
DOI	10.1109/ICCAD.1990.129851
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-11-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Pins Shape Topology Laboratories Upper bound Delay Timing Quality management
Content Type	Text
Resource Type	Article

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