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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shiraishi, Y. Kimura, M. Kobayashi, K. Hino, T. Seriuchi, M. Kusaoke, M. |
| Copyright Year | 1990 |
| Description | Author affiliation: Hitachi Ltd., Tokyo, Japan (Shiraishi, Y.; Kimura, M.; Kobayashi, K.; Hino, T.) |
| Abstract | Efficient placement and routing algorithms are presented for the modules of a bipolar analog LSI. In the layout of an analog module, a grid-free technique is required to minimize the module area and geometric constraint observance is necessary for the circuit performance optimization. The placement algorithm determines cell positions observing the geometric constraints by vertex-grouping of the constraint graph representing the relative device positions in the input circuit diagram. The routing algorithm, based on the characteristic fine-grid maze router, allows grid-free routing and variable width routings observing the geometric constraints by dynamically generating wiring prohibition. These algorithms are applied to the design of the analog modules. Automatically designed modules are compact and the performance requirements are met.< |
| Starting Page | 194 |
| Ending Page | 197 |
| File Size | 399302 |
| Page Count | 4 |
| File Format | |
| ISBN | 0818620552 |
| DOI | 10.1109/ICCAD.1990.129878 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1990-11-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Large scale integration Routing Very large scale integration Constraint optimization Wiring Solid modeling Resistors Capacitors Circuit optimization Mesh generation |
| Content Type | Text |
| Resource Type | Article |
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