NDLI: VLSI placement using uncertain costs

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A routing algorithm for harvesting multipipeline arrays with small intercell and pipeline delays

Topological routing using geometric information

An optimal channel pin assignment algorithm

Constraint identification for timing verification

Race detection for two-phase systems

Timing constraints for correct performance

An automata-theoretic approach to behavioral equivalence

Tautology checking using cross-controllability and cross-observability relations

Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams

A new global router based on a flow model and linear assignment

A timing-driven global router for custom chip design

Rubber band routing and dynamic data representation

Touch and cross router

Exploitation of periodicity in logic simulation of synchronous circuits

SNEL: a switch-level simulator using multiple levels of functional abstraction

Optimization of the parallel technique for compiled unit-delay simulation

Fast switch-level fault simulation using functional fault modeling

An algorithm for nearly-minimal collapsing of finite-state machine networks

Implicit state transition graphs: applications to sequential logic synthesis and test

Minimization of symbolic relations

Algorithms for discrete function manipulation

Floorplanning with pin assignment

Diffusion-an analytic procedure applied to macro cell placement

Floorplanning by topological constraint reduction

Design for circuit quality: yield maximization, minimax, and Taguchi approach

Computing parametric yield accurately and efficiently

Accurate and efficient evaluation of circuit yield and yield gradients

A unified framework for the formal verification of sequential circuits

Implicit state enumeration of finite state machines using BDD's

ATPG aspects of FSM verification

FOLM-planner: A new floorplanner with a frame overlapping floorplan model suitable for SOG (sea-of-gates) type gate arrays

Partitioning algorithms for layout synthesis from register-transfer netlists

A robust framework for hierarchical floorplanning with integrated global wiring

GRCA: a global approach for floorplanning synthesis in VLSI macrocell design

Mixed-mode incremental simulation and concurrent fault simulation

Incorporation of inductors in piecewise approximate circuit simulation

Analysis of VLSI multiconductor systems by bi-level waveform relaxation

Measuring error propagation in waveform relaxation algorithms

Extraction of functional information from combinational circuits

An O(n/sup 3/logn)-heuristic for microcode bit optimization

Optimized synthesis of asynchronous control circuits from graph-theoretic specifications

High-level delay estimation for technology-independent logic equations

A high-packing density module generator for bipolar analog LSIs

Constraint-based channel routing for analog and mixed analog/digital circuits

A routing methodology for analog integrated circuits

The component synthesis algorithm: technology mapping for register transfer descriptions

MOSP: module selection for pipelined designs with multi-cycle operations

Partitioning of functional models of synchronous digital systems

Contest: a fast ATPG tool for very large combinational circuits

A single-state-transition fault model for sequential machines

Mixed-level sequential test generation using a nine-valued relaxation algorithm

A parallel algorithm for hierarchical circuit extraction

A hierarchical circuit extractor based on new cell overlap analysis

XREF coupling: capacitive coupling error checker

Preform: a process independent symbolic layout system

Exploiting the special structure of conflict and compatibility graphs in high-level synthesis

A global optimization approach for architectural synthesis

SALSA: a new approach to scheduling with timing constraints

A hierarchical approach for testing large circuits

On the efficiency of the transition fault model for delay faults

Evaluation and synthesis of self-monitoring state machines

QUIETEST: a quiescent current testing methodology for detecting leakage faults

CADICS-cyclic analog-to-digital converter synthesis

A usable circuit optimizer for designers

Optimal test set design for analog circuits

Feedback-driven datapath optimization in Fasolt

Automatic high level synthesis of partitioned busses

Data path construction and refinement

Partial scan by use of empirical testability

Test vector minimization during logic synthesis

On determining scan flip-flops in partial-scan designs

A fast algorithm for performance-driven placement

Congestion-driven placement using a new multi-partitioning heuristic

New algorithms for the placement and routing of macro cells

VLSI placement using uncertain costs

Distributed methodology management for design-in-the-large

Knowledge based design flow management

A CAD process scheduling technique

A history model for managing the VLSI design process

On the diagnostic resolution of signature analysis

Computing the error escape probability in count-based compaction schemes

Partial detectability profiles

A routing system for mixed A/D standard cell LSI's

A detailed router for field-programmable gate arrays

Three-dimensional routing for multilayer ceramic printed circuit boards

Simulating electromagnetic radiation of printed circuit boards

SIMCURRENT-an efficient program for the estimation of the current flow of complex CMOS circuits

An integrated hot-carrier degradation simulator for VLSI reliability analysis

Multi-level logic minimization across latch boundaries

Performance optimization of pipelined circuits

Don't care minimization of multi-level sequential logic networks

A clock net reassignment algorithm using Voronoi diagram

An exact algorithm for single-layer wire-length minimization

A new class of Steiner tree heuristics with good performance: the iterated 1-Steiner approach

Rectilinear Steiner tree construction by local and global refinement

Circuit simulation algorithms on a distributed memory multiprocessor system

Parallel simulation algorithms for grid-based analog signal processors

A parallel block-diagonal preconditioned conjugate-gradient solution algorithm for circuit and device simulations

Fast overlapped scattered array storage schemes for sparse matrices

Testability-preserving circuit transformations

Timing optimization with testability considerations

Efficient automatic diagnosis of digital circuits

An algorithm for locating logic design errors

Logic compilation from graphical dependency notation

HS: a hierarchical search package for CAD data

A data flow based architecture for CAD frameworks

An algebra for switch-level simulation

A new method for assigning signal flow directions to MOS transistors

Logic simulation and parallel processing

Observability don't care sets and Boolean relations

PHIFACT-a Boolean preprocessor for multi-level logic synthesis

A method for concurrent decomposition and factorization of Boolean expressions

A two-level two-way partitioning algorithm

Finding clusters in VLSI circuits

Optimal orientations of transistor chains

A new template based approach to module generation

AWEsim: a program for the efficient analysis of linear(ized) circuits

Efficient pole zero sensitivity calculation in AWE

Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique

DC parameterized piecewise-function transistor models for bipolar and MOS logic stage delay evaluation

CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits

A framework environment for logic design support system

MIS-MV: optimization of multi-level logic with multiple-values inputs

Multi-level logic optimization for large scale ASICs

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.90CH2924-9)

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

VLSI placement using uncertain costs

Content Provider	IEEE Xplore Digital Library
Author	Harkness, C.L. Lopresti, D.P.
Copyright Year	1990
Description	Author affiliation: Dept. of Comput. Sci., Brown Univ., Providence, RI, USA (Harkness, C.L.; Lopresti, D.P.)
Abstract	Many objective functions used to evaluate placement quality contain uncertain parameters (e.g. channel width, wire length). While these values can be estimated, they cannot be precisely known until the layout is finished. As a result, current automatic placement algorithms use 'expected' values in their objective functions and return one possible estimate of placement quality. An algorithm that uses the full range of potential values when computing placement cost can yield a more credible prediction of placement quality and reveal more about the structure of optimal configurations. An interval-based approach to modeling uncertainty in automatic placement is proposed. It is used to illustrate the authors' methods by implementing an interval branch and bound placement algorithm.<>
Starting Page	340
Ending Page	343
File Size	314865
Page Count	4
File Format	PDF
ISBN	0818620552
DOI	10.1109/ICCAD.1990.129919
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-11-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Circuits Uncertainty Cost function Wire Routing Delay Iterative algorithms Partitioning algorithms Computer science
Content Type	Text
Resource Type	Article

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