NDLI: Data path construction and refinement

Content Provider	IEEE Xplore Digital Library
Author	Fur-Shing Tsai Yu-Chin Hsu
Copyright Year	1990
Description	Author affiliation: Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan (Fur-Shing Tsai; Yu-Chin Hsu)
Abstract	A system is described for the data path allocation problem in digital signal processor synthesis. The system, STAR, consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The actions taken in each phase are described. The authors' contributions include the following: (1) theorems for the lower bound of the number of interconnections; (2) in the DPR phase, a more global view of the allocation problem is taken by ripping up and reallocating different types of objects simultaneously; (3) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources which the object uses; (4) a method to judge the potential for upgrading a data path; and (5) an iterative improvement technique based on the idea of a relation network. The system currently supports the synthesis of architecture in linear topology and random topology. Parameters can be specified to explore different design alternatives and design space. Experiments on benchmarks show promising results.<>
Starting Page	308
Ending Page	311
File Size	381800
Page Count	4
File Format	PDF
ISBN	0818620552
DOI	10.1109/ICCAD.1990.129910
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-11-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Topology Scheduling Resource management Hardware Computer science Digital signal processors Signal synthesis Data structures Iterative methods Control system synthesis
Content Type	Text
Resource Type	Article

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