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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Liangge Xu Lindfors, S. Ryynanen, J. |
| Copyright Year | 2008 |
| Description | Author affiliation: Electron. Circuit Design Lab., Helsinki Univ. of Technol., Helsinki (Liangge Xu; Lindfors, S.; Ryynanen, J.) |
| Abstract | This paper proposes a technique to speed up the start-up process of frequency synthesizers for wireless sensor network (WSN) applications. The proposed technique relies on an all-digital phase-locked loop (ADPLL) architecture to preserve last known settled synthesizer state over an extended power-down period and use it on next power-up. The effect of periodic variations such as a change in die temperature is digitally compensated for by utilizing a simple least mean-square (LMS) adaptation algorithm. Simulations demonstrate that with slow ambient temperature drift, the start-up time of the frequency synthesizer can be dramatically reduced. |
| Starting Page | 388 |
| Ending Page | 391 |
| File Size | 345231 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424421817 |
| DOI | 10.1109/ICECS.2008.4674872 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-31 |
| Publisher Place | Malta |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Radio frequency Phase locked loops Wireless sensor networks Frequency synthesizers Temperature sensors Energy consumption Low pass filters Least squares approximation Bandwidth Circuits |
| Content Type | Text |
| Resource Type | Article |
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