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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jutman, A. Aleksejev, I. Raik, J. Ubar, R. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Comp. Eng., Tallinn Univ. of Technol., Tallinn (Jutman, A.; Aleksejev, I.; Raik, J.; Ubar, R.) |
| Abstract | Built-In Self-Test (BIST) techniques are often based on pseudo-random pattern generators, which represent simple structures that can generate necessary test stimuli for a device under test (DUT). For some designs, however, additional measures of fault coverage improvement have to be applied. LFSR reseeding is a popular technique due to its ability to considerably improve both the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. Proper selection of LFSR seeds is the key aspect in a successful reseeding scheme. In this paper, we present our approach to reseeding optimization that is based on compaction of pre-generated LFSR sub-sequences in order to select a minimal subset of to be included into the final solution. The proposed approach relies on the branch-and-bound search technique, which can provide the optimal compaction for a given test setup. Alternatively, it can run for a limited time in a heuristic mode, producing intermediate results. Experiments show that applied heuristics can yield optimal or quasi-optimal solutions in polynomial time. These solutions outperform previously published results for a similar reseeding approach. |
| Starting Page | 1290 |
| Ending Page | 1295 |
| File Size | 303166 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424421817 |
| DOI | 10.1109/ICECS.2008.4675096 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-31 |
| Publisher Place | Malta |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Compaction Automatic test pattern generation Built-in self-test Circuit faults Test pattern generators Automatic testing Hardware High speed integrated circuits Semiconductor device manufacture Electronic equipment testing |
| Content Type | Text |
| Resource Type | Article |
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