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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yanhui Li Fernando, S.D. Heng Yu Xiaolei Chen Yajun Ha Teng Tiow Tay |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore (Yanhui Li; Fernando, S.D.; Heng Yu; Xiaolei Chen; Yajun Ha; Teng Tiow Tay) |
| Abstract | Caches in embedded systems improve average case performance, but they are a source of unpredictability, especially in the worst case software timing analysis with the consideration of data caches. This is a critical problem in real-time systems, where tight worst case execution time (WCET) is required for their schedulability analysis. Several works have studied the data cache impacts on the WCET of programs, but they can only handle programs with no input dependent data accesses. To solve this problem, we have developed a novel architecture and a WCET analysis framework for this architecture. Our work classifies predictable and unpredictable accesses and allocates them into predictable caches and unpredictable caches respectively, using the CME (cache miss equations) and reuse-distance based algorithms accordingly. The analysis framework produces a very good WCET tightness compared with simulations, and our architecture creates almost no hardware overhead or performance degradation. |
| Starting Page | 410 |
| Ending Page | 413 |
| File Size | 203703 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424421817 |
| DOI | 10.1109/ICECS.2008.4674877 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-31 |
| Publisher Place | Malta |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Memory architecture Performance analysis Embedded system Embedded software Software performance Timing Real time systems Equations Analytical models Hardware |
| Content Type | Text |
| Resource Type | Article |
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