NDLI: An ultra low-power CMOS frequency synthesizer for low data-rate sub-GHz applications

Content Provider	IEEE Xplore Digital Library
Author	Ippolito, C.M. Italia, A. Palmisano, G.
Copyright Year	2010
Description	Author affiliation: Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Università di Catania, Facoltà di Ingegneria, DIEES, V.le A. Doria 6, 95125, Italy (Ippolito, C.M.; Italia, A.; Palmisano, G.)
Abstract	An ultra low-power frequency synthesizer for sub-GHz applications was designed and implemented in a 90-nm CMOS technology. Based on an integer-N phase-locked loop architecture, the frequency synthesizer covers the 0.3–0.95 GHz band almost continuously with 150-kHz channel steps. Multi-band operation is achieved thanks to a wideband low-power LC VCO, which makes use of shunt-connected switched-coupled inductors. Power consumption has been minimized by adopting true single-phase clocked logic cells for the first stages of the programmable divider. The frequency synthesizer achieves a phase noise of −96 dBc/Hz at 150-kHz offset frequency. The measured settling time is around 350 µS and the reference spurs are lower than −52 dBc. The circuit power consumption is only 1.8 mW from a 1.2-V supply.
Starting Page	1
Ending Page	4
File Size	863665
Page Count	4
File Format	PDF
ISBN	9781424479054
e-ISBN	9783981375404
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	VDE
Subject Keyword	Phase noise Frequency synthesizers wireless sensor networks Voltage-controlled oscillators ultra low-power circuits phase-locked loops (PLLs) frequency synthesizers Generators CMOS integrated circuits medical services Phase locked loops Tuning
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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