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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kuo-Hsing Cheng Hsin-Hao Wang Ding-Jyun Huang |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electr. Eng., Nat. Central Univ., Jhongli (Kuo-Hsing Cheng; Hsin-Hao Wang; Ding-Jyun Huang) |
| Abstract | This paper describes a 2GS/s 10 bit DAC with a supply voltage lower to 1 volt. It has been realized in a 90-nm 1P9M CMOS technology. A novel high precision active cascode mirror circuit is presented. Provided the headroom is not affected, operating the current source in the triode region, the precision of the current source array can be obtained. In addition, the demand of low analog/digital supply voltage and the influence of MOS short-channel effect can be overcome. The INL is between +0.12 and -0.14 LSB, and the DNL is between +0.23 and -0.35 LSB. When the DAC operates at an input signal frequency of 10 MHz, a SFDR of 65.1 dB can be achieved. Moreover, a SFDR of 54.4 dB can be gained when the DAC operates at 982.2 MHz. The power consumption of the proposed design is approximately 79 mW. The chip area is about 1 mm times 1 mm. |
| Starting Page | 340 |
| Ending Page | 343 |
| File Size | 471654 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424421817 |
| DOI | 10.1109/ICECS.2008.4674860 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-31 |
| Publisher Place | Malta |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS technology Circuits Mirrors Switches Impedance Low voltage Flip-flops Decoding Frequency synchronization Energy consumption |
| Content Type | Text |
| Resource Type | Article |
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