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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kyung-Ju Cho Suhyun Jo Yong-Eun Kim Yi-Nan Xu Jin-Gyun Chung |
| Copyright Year | 2008 |
| Description | Author affiliation: Div. of Electron.&Inf. Eng., Chonbuk Nat. Univ., Jeonju (Kyung-Ju Cho; Suhyun Jo; Yong-Eun Kim; Yi-Nan Xu; Jin-Gyun Chung) |
| Abstract | The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-24 FFT example, it is shown that the area, speed and power consumption can be reduced up to 21%, 11% and 12%, respectively, by the proposed algorithm. |
| Starting Page | 41 |
| Ending Page | 44 |
| File Size | 274369 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424421817 |
| DOI | 10.1109/ICECS.2008.4674786 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-31 |
| Publisher Place | Malta |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Signal processing algorithms Energy consumption Digital signal processing Discrete cosine transforms Design methodology Algorithm design and analysis Signal design Adders Design engineering Hardware |
| Content Type | Text |
| Resource Type | Article |
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