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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Siew Han Looe Soon Wei Wang Aripin, A. |
| Copyright Year | 2007 |
| Description | Author affiliation: ON Semicond., Seremban (Siew Han Looe; Soon Wei Wang; Aripin, A.) |
| Abstract | The current and future market demand for small, portable, compact and multi functional electronic products raises a great challenge to the semiconductor industries for small and thin package size, high quality, and high performance. The drive for package thickness thinning and package size reduction has created new challenges for current wire bonding technology which has led to small ball and low loop profile with largest possible wire size for the advantage of electrical performance. In the course of qualifying one of the ultra thin QFN (Quad Flat No-lead) small packages, gross heel stress was found at certain wire location in a high defect rate. First attempt in optimizing the wire bond power does not solve the heel stress problem. This indicates the complexity of the issue with existence of other significant influencing factors. DMAIC Methodology has been used to approach the problem in detail level. Several statistical analysis, design of experiment (DOE) and Finite Element Analysis (FEA) have been performed in order to narrow down to vital few. The FEA analysis in wire resonance has led the team to detail experiments in wire bonding sequence. Thorough analysis (through DOEs and statistical analysis) has been performed to identify the most optimized looping profile in distributing the ultrasonic power effectively. Package layout is fully explored as well to identify opportunities in improving the robustness of wire bonding. This paper explains in detail the hypothesis, statistical analysis, DOEs and FEA that have been performed to identify the root causes of this particular heel stress issue using DMAIC methodology. It is proven that the convergence of data driven and experience driven analysis through DMAIC methodology is the key to the success of this project. The convincing result shows that lead frame design, wire bonding direction, sequence, and loop profile are significant factors. This paper also illustrates all the solutions employed not only to eliminate the heel stress problem, but to enhance robustness in wire bonding as well. |
| Starting Page | 28 |
| Ending Page | 33 |
| File Size | 4201625 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424413355 |
| ISSN | 10898190 |
| DOI | 10.1109/IEMT.2007.4417051 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-10-03 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stress Wire Bonding Electronics packaging Semiconductor device packaging Statistical analysis Performance analysis Robustness Consumer electronics Industrial electronics |
| Content Type | Text |
| Resource Type | Article |
| Subject | Industrial and Manufacturing Engineering Electrical and Electronic Engineering |
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