NDLI: Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET

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Moore's law at 50: Are we planning for retirement?

Quantum computing in silicon

Silicon for prevention, cure and care: A technology toolbox of wearables at the dawn of a new health system

First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters

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Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET

Content Provider	IEEE Xplore Digital Library
Author	Avci, Uygar E. Chu-Kung, Benjamin Agrawal, Ashish Dewey, Gilbert Le, Van Rios, Rafael Morris, Daniel H. Hasan, Sayed Kotlyar, Roza Kavalieros, Jack Young, Ian A.
Copyright Year	2015
Description	Author affiliation: Components Research, Technology and Manufacturing Group, Intel Corporation, Hillsboro, OR, USA (Avci, Uygar E.; Chu-Kung, Benjamin; Agrawal, Ashish; Dewey, Gilbert; Le, Van; Rios, Rafael; Morris, Daniel H.; Kavalieros, Jack; Young, Ian A.) \|\| Portland Technology Development, Technology and Manufacturing Group, Intel Corporation, Hillsboro, OR, USA (Hasan, Sayed; Kotlyar, Roza)
Abstract	Tunneling Field Effect Transistor (TFET) has attracted interest due to its steep-SS prospects [1]. Although a number of sub-60mV/dec TFETs were demonstrated [2], many failed to realize this feat due to non-optimized geometry, material choice [3], and material defects [4, 5]. In this paper, we clearly distinguish the requirement for i) geometry, ii) semiconductor BTBT characteristics, iii) semiconductor defects and iv) oxide interface defects. Using Ge as a case study, multi-temperature characterization of experimental PIN diodes is used to separate bulk properties from the interface effects, calibrating the models for BTBT, trap-assisted-tunneling (TAT) and SRH. The measured BTBT characteristic of a material is as important as the effect of defects; even a zero-defect TFET using the calibrated Ge material requires thin body and thin oxide. Bulk SRH and TAT is found to be a less critical issue for thin body TFETs, whereas interface defect density ∼1012cm−2 is low enough to only degrade TFET SS <10mV/dec. The method of current component segmentation using multi-temperature short-intrinsic PIN diodes is essential for evaluation of materials for TFETs.
File Size	1403082
File Format	PDF
ISSN	2156017X
e-ISBN	9781467398947
DOI	10.1109/IEDM.2015.7409828
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tunneling Semiconductor diodes Geometry Temperature dependence Temperature Floors
Content Type	Text
Resource Type	Article

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