NDLI: Improvement of characteristics of NbO2 selector and full integration of 4F2 2x-nm tech 1S1R ReRAM

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Moore's law at 50: Are we planning for retirement?

Quantum computing in silicon

Silicon for prevention, cure and care: A technology toolbox of wearables at the dawn of a new health system

First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters

Experimental study on carrier transport properties in extremely-thin body Ge-on-insulator (GOI) p-MOSFETs with GOI thickness down to 2 nm

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

Germanium-based transistors for future high performance and low power logic applications

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Direct bandgap GeSn microdisk lasers at 2.5 μm for monolithic integration on Si-platform

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The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown

Novel fast-switching and high-data retention phase-change memory based on new Ga-Sb-Ge material

Crystalline-as-deposited ALD phase change material confined PCM cell for high density storage class memory

Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures

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Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power)

Memristive based device arrays combined with Spike based coding can enable efficient implementations of embedded neuromorphic circuits

A mixed-signal universal neuromorphic computing system

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DARPA neurocomputing

Physical modeling — A new paradigm in device simulation

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Numerical investigation of the lateral and vertical leakage currents and breakdown regimes in GaN-on-Silicon vertical structures

Oxide-based RRAM: Requirements and challenges of modeling and simulation

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High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

TFT backplane technologies for advanced array applications

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Mapping of wafer-level plasma induced charge contour by novel on-chip in-situ recorders in advance FinFET technologies

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A new insight into BEOL TDDB lifetime model for advanced technology scaling

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Advanced device performance impact by wafer level 3D stacked architecture

New challenges and opportunities for 3D integrations

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Collapse-free high power InAlGaN/GaN-HEMT with 3 W/mm at 96 GHz

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Non volatile memory evolution and revolution

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Improvement of characteristics of NbO2 selector and full integration of 4F2 2x-nm tech 1S1R ReRAM

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Charge transport modelling in organic semiconductors: From diodes to transistors, memories and energy harvesters

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200mm GaN-on-Si epitaxy and e-mode device technology

High-K gate dielectric depletion-mode and enhancement-mode GaN MOS-HEMTs for improved OFF-state leakage and DIBL for power electronics and RF applications

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Improvement of characteristics of NbO2 selector and full integration of 4F2 2x-nm tech 1S1R ReRAM

Content Provider	IEEE Xplore Digital Library
Author	Kim, Soo Gil Ha, Tae Jung Kim, Seonghyun Lee, Jae Yeon Kim, Kyung Wan Shin, Jung Ho Park, Yong Taek Song, Suk Pyo Kim, Beom Yong Kim, Wan Gee Lee, Jong Chul Lee, Hyun Sun Song, Jong Ho Hwang, Eung Rim Cho, Sang Hoon Ku, Ja Chun Kim, Jong Il Kim, Kyu Sung Yoo, Jong Hee Kim, Hyo Jin Jung, Hoe Gwon Lee, Kee Jeung Chung, Suock Kang, Jong Ho Lee, Jung Hoon Kim, Hyeong Soo Hong, Sung Joo Gibson, Gary Jeon, Yoocharn
Copyright Year	2015
Description	Author affiliation: R&D division, SK Hynix Inc., 2091 Gyeongchung-daero Bubal-eub, Icheon-si Gyeonggi-do, Korea, 467-701 (Kim, Soo Gil; Ha, Tae Jung; Kim, Seonghyun; Lee, Jae Yeon; Kim, Kyung Wan; Shin, Jung Ho; Park, Yong Taek; Song, Suk Pyo; Kim, Beom Yong; Kim, Wan Gee; Lee, Jong Chul; Lee, Hyun Sun; Song, Jong Ho; Hwang, Eung Rim; Cho, Sang Hoon; Ku, Ja Chun; Kim, Jong Il; Kim, Kyu Sung; Yoo, Jong Hee; Kim, Hyo Jin; Jung, Hoe Gwon; Lee, Kee Jeung; Chung, Suock; Kang, Jong Ho; Lee, Jung Hoon; Kim, Hyeong Soo; Hong, Sung Joo) \|\| HP laboratories, 1501 Page Mill Rd., Palo Alto, CA, USA 94304 (Gibson, Gary; Jeon, Yoocharn)
Abstract	In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was characterized with the integration of selector and resistor materials.
File Size	1702637
File Format	PDF
ISSN	2156017X
e-ISBN	9781467398947
DOI	10.1109/IEDM.2015.7409668
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors Current measurement Switches Films Transistors CMOS integrated circuits CMOS technology
Content Type	Text
Resource Type	Article

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