NDLI: Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs

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2015 IEEE International Electron Devices Meeting (IEDM)

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Moore's law at 50: Are we planning for retirement?

Quantum computing in silicon

Silicon for prevention, cure and care: A technology toolbox of wearables at the dawn of a new health system

First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters

Experimental study on carrier transport properties in extremely-thin body Ge-on-insulator (GOI) p-MOSFETs with GOI thickness down to 2 nm

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

Germanium-based transistors for future high performance and low power logic applications

A novel two-varistors (a-Si/SiN/a-Si) selected complementary atom switch (2V-1CAS) for nonvolatile crossbar switch with multiple fan-outs

Direct bandgap GeSn microdisk lasers at 2.5 μm for monolithic integration on Si-platform

MOVPE In1−xGaxAs high mobility channel for 3-D NAND memory

A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity

A floating gate based 3D NAND technology with CMOS under array

The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown

Novel fast-switching and high-data retention phase-change memory based on new Ga-Sb-Ge material

Crystalline-as-deposited ALD phase change material confined PCM cell for high density storage class memory

Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures

Neuromorphic architectures for spiking deep neural networks

Development of a neuromorphic computing system

Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power)

Memristive based device arrays combined with Spike based coding can enable efficient implementations of embedded neuromorphic circuits

A mixed-signal universal neuromorphic computing system

Oxide based nanoscale analog synapse device for neural signal recognition system

"What the brain tells us about the future of silicon"

DARPA neurocomputing

Physical modeling — A new paradigm in device simulation

Ab initio study of avalanche breakdown in diamond for power device applications

Numerical investigation of the lateral and vertical leakage currents and breakdown regimes in GaN-on-Silicon vertical structures

Oxide-based RRAM: Requirements and challenges of modeling and simulation

Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

Statistical poly-Si grain boundary model with discrete charging defects and its 2D and 3D implementation for vertical 3D NAND channels

Carrier transport analysis of high-performance poly-Si Nanowire transistor fabricated by advanced SPC with record-high electron mobility

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

TFT backplane technologies for advanced array applications

20-nm-Node trench-gate-self-aligned crystalline In-Ga-Zn-Oxide FET with high frequency and low off-state current

Extremely high mobility ultra-thin metal-oxide with ns2np2 configuration

Oxide thin film transistor technology: Capturing device-circuit interactions

Mapping of wafer-level plasma induced charge contour by novel on-chip in-situ recorders in advance FinFET technologies

A novel method to characterize the effect from the diffusion of Cu in through silicon via (TSV)

A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits

A new insight into BEOL TDDB lifetime model for advanced technology scaling

Intrinsic program instability in HfO2 RRAM and consequences on program algorithms

Cycling-induced degradation of metal-oxide resistive switching memory (RRAM)

Distribution projecting the reliability for 40 nm ReRAM and beyond based on stochastic differential equation

Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes

Novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using ultra-high density nano-Cu filaments for exascale 2.5D/3D integration

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

Advanced device performance impact by wafer level 3D stacked architecture

New challenges and opportunities for 3D integrations

Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

Enabling low power BEOL compatible monolithic 3D+ nanoelectronics for IoTs using local and selective far-infrared ray laser anneal technology

Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs

Collapse-free high power InAlGaN/GaN-HEMT with 3 W/mm at 96 GHz

High frequency high breakdown voltage GaN transistors

26.5 Terahertz electrically triggered RF switch on epitaxial VO2-on-Sapphire (VOS) wafer

Enhancement-mode GaN double-channel MOS-HEMT with low on-resistance and robust gate recess

A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems

GaNFET compact model for linking device physics, high voltage circuit design and technology optimization

GaN-on-GaN p-n power diodes with 3.48 kV and 0.95 mΩ-cm2: A record high figure-of-merit of 12.8 GW/cm2

Non volatile memory evolution and revolution

Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells

Improvement of characteristics of NbO2 selector and full integration of 4F2 2x-nm tech 1S1R ReRAM

Cu BEOL compatible selector with high selectivity (>107), extremely low off-current (∼pA) and high endurance (>1010)

1Kbit FinFET Dielectric (FIND) RRAM in pure 16nm FinFET CMOS logic process

Programming-conditions solutions towards suppression of retention tails of scaled oxide-based RRAM

Comprehensive assessment of RRAM-based PUF for hardware security applications

2RW dual-port SRAM design challenges in advanced technology nodes

Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell

Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin

Magnetic thin-film inductors for monolithic integration with CMOS

Reliability variability simulation methodology for IC design: An EDA perspective

Self-heating on bulk FinFET from 14nm down to 7nm node

Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization — New findings on the layout dependent aging effects

Phonon-limited performance of single-layer, single-gate black phosphorus n- and p-type field-effect transistors

Effects of interlayer interaction in van der Waals layered black phosphorus for sub-10 nm FET

Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI

How good is mono-layer transition-metal dichalcogenide tunnel field-effect transistors in sub-10 nm? — An ab initio simulation study

A computational study of van der Waals tunnel transistors: Fundamental aspects and design challenges

Charge transport modelling in organic semiconductors: From diodes to transistors, memories and energy harvesters

Understanding the nature of metal-graphene contacts: A theoretical and experimental study

Ultra-low power sensing platform for personal health and personal environmental monitoring

Highly integrated CMOS microsystems to interface with neurons at subcellular resolution

High throughput cell sorter based on lensfree imaging of cells

Lensfree microscopy: A new framework for the imaging of viruses, bacteria, cells and tissue

Precision mass measurements in solution reveal properties of single cells and bioparticles

Fabrication and analysis of SiN nanopores for direct DNA sequencing

Scalpel soft retrace scanning spreading resistance microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET

Tunnel junction abruptness, source random dopant fluctuation and PBTI induced variability analysis of GaAs0.4Sb0.6/In0.65Ga0.35As heterojunction tunnel FETs

Understanding of BTI for tunnel FETs

ESD characterization of gate-all-around (GAA) Si nanowire devices

On and off state hot carrier reliability in junctionless high-K MG gate-all-around nanowires

Structural coordination of rigidity with flexibility in gate dielectric films for sub-nm EOT Ge gate stack reliability

Time dependent threshold-voltage fluctuations in NAND flash memories: From basic physics to impact on array operation

A single-electron analysis of NAND flash memory programming

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

InGaAs 3D MOSFETs with drastically different shapes formed by anisotropic wet etching

Novel wafer-scale uniform layer-by-layer etching technology for line edge roughness reduction and surface flattening of 3D Ge channels

Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules

Present status and future prospects of nano-carbon interconnect technologies for LSIs

High-performance photonic BiCMOS process for the fabrication of high-bandwidth electronic-photonic integrated circuits

Application-oriented performance of RF CMOS technologies on flexible substrates

State-of-the-art GaN vertical power devices

200mm GaN-on-Si epitaxy and e-mode device technology

High-K gate dielectric depletion-mode and enhancement-mode GaN MOS-HEMTs for improved OFF-state leakage and DIBL for power electronics and RF applications

Renovation of power devices by GaN-based materials

From epitaxy to converters topologies what issues for 200 mm GaN/Si?

Advanced power electronic devices based on Gallium Nitride (GaN)

Increasing the switching frequency of GaN HFET converters

SiC- and GaN-based power devices: Technologies, products and applications

NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2−x/Pt Memristors

Efficient in-memory computing architecture based on crossbar arrays

High density neuromorphic system with Mo/Pr0.7Ca0.3MnO3 synapse and NbO2 IMT oscillator neuron

Optimized learning scheme for grayscale image recognition in a RRAM based analog neuromorphic system

Gate/Source overlapped heterojunction tunnel FET for non-Boolean associative processing with plasticity

Energy-delay performance optimization of NEM logic relay

A two-gap capacitive structure for high aspect-ratio capacitive sensor arrays

Polysilicon nanowire NEMS fabricated at low temperature for above IC NEMS mass sensing applications

A reliable CMOS-MEMS platform for titanium nitride composite (TiN-C) resonant transducers with enhanced electrostatic transduction and frequency stability

Spurious mode suppression in SH0 Lithium Niobate laterally vibrating MEMS resonators

Super high frequency lithium niobate surface acoustic wave transducers up to 14 GHz

Output enhancement of triboelectric energy harvester by micro-porous triboelectric layer

Flexible electronics for commercial and defense applications

Materials and design considerations for fast flexible and stretchable electronics

ACF-packaged ultrathin Si-based flexible NAND flash memory

Free form CMOS electronics: Physically flexible and stretchable

Large area sensing surfaces: Flexible organic printed interfacing circuits and sensors

ZnO thin film transistors for more than just displays

Organic thin film transistors for flexible electronics

Flexible 2D FETs using hBN dielectrics

Gate-sided hydrogen release as the origin of "permanent" NBTI degradation: From single defects to lifetimes

Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies

Fundamental trade-off between short-channel control and hot carrier degradation in an extremely-thin silicon-on-insulator (ETSOI) technology

Hot carrier aging and its variation under use-bias: Kinetics, prediction, impact on Vdd and SRAM

Technology scaling and reliability: Challenges and opportunities

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array

Implications of variability on resilient design

Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology

Variation improvement for manufacturable FINFET technology

Enhanced sub 20-nm FinFET performance by stacked gate dielectric with less oxygen vacancies featuring higher current drive capability and superior reliability

Self-decomposition of SiO2 due to Si-chemical potential increase in SiO2 between HfO2 and substrate — Comprehensive understanding of SiO2-IL scavenging in HfO2 gate stacks on Si, SiGe and SiC

Preferential oxidation of Si in SiGe for shaping Ge-rich SiGe gate stacks

Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation

1.5×10−9 Ωcm2 Contact resistivity on highly doped Si:P using Ge pre-amorphization and Ti silicidation

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

Tunneling field effect transistors: Device and circuit considerations for energy efficient logic opportunities

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

Novel SiGe/Si line tunneling TFET with high Ion at low Vdd and constant SS

Quantifying the impact of gate efficiency on switching steepness of quantum-well tunnel-FETs: Experiments, modeling, and design guidelines

Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies

Sub-60mV-swing negative-capacitance FinFET without hysteresis

Super steep subthreshold slope PN-body tied SOI FET with ultra low drain voltage down to 0.1V

MTJ-based "normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and last level cache based on 1T-1MTJ cell and novel error handling scheme

High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology

A 3/5 GHz reconfigurable CMOS low-noise amplifier integrated with a four-terminal phase-change RF switch

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

New devices for internet of things: A circuit level perspective

Robust and compact key generator using physically unclonable function based on logic-transistor-compatible poly-crystalline-Si channel FinFET technology

An integrated silicon photonics technology for O-band datacom

150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET

Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications

Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond

STT-MRAM with double magnetic tunnel junctions

Solving the paradox of the inconsistent size dependence of thermal stability at device and chip-level in perpendicular STT-MRAM

20nm DRAM: A new beginning of another revolution

Gate-first high-k/metal gate DRAM technology for low power and high performance products

A novel Bi-stable 1-transistor SRAM for high density embedded applications

Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multi-level FeFET memory cells

The challenging promise of 2D materials for electronics

Epitaxial CVD growth of high-quality graphene and recent development of 2D heterostructures

2D layered materials: From materials properties to device applications

High-frequency, scaled MoS2 transistors

Bandgap engineering in 2D layered materials

van der Waals junctions of layered 2D materials for functional devices

Roll-to-roll synthesis and patterning of graphene and 2D materials

Transport mechanism in sub 100°C processed high mobility polycrystalline ZnO transparent thin film transistors

Physical-based analytical model of flexible a-IGZO TFTs accounting for both charge injection and transport

Predictive compact modeling of random variations in FinFET technology for 16/14nm node and beyond

A new surface potential based physical compact model for GFET in RF applications

Physics-based compact modeling framework for state-of-the-art and emerging STT-MRAM technology

Physics-based compact modeling of charge transport in nanoscale electronic devices

Field-effect control of ions beyond debye-screening limit in nanofluidic transistors

High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC

1.3 Mega pixels CCD pH imaging sensor with 3.75 μm spatial resolution

A microfabricated electronic microplate platform for low-cost repeatable biosensing applications

High-density optrode-electrode neural probe using SixNy photonics for in vivo optogenetics

An ultra thin implantable system for cerebral blood volume monitoring using flexible OLED and OPD

An ultraflexible microbubble blood pressure sensor for interventional treatment

Multi-storied photodiode CMOS image sensor for multiband imaging with 3D technology

First demonstration of 0.9 μm pixel global shutter operation by novel charge control in organic photoconductive film

Color image sensor with organic photoconductive films

Optical performance study of BSI image sensor with stacked grid structure

Avalanche photodiode featuring Germanium-tin multiple quantum wells on silicon: Extending photodetection to wavelengths of 2 and beyond

High dose efficiency, ultra-high resolution amorphous selenium/CMOS hybrid digital X-ray imager

Stacked image sensor using chlorine-doped crystalline selenium photoconversion layer composed of size-controlled polycrystalline particles

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Quantum-size effects in sub 10-nm fin width InGaAs FinFETs

Single suspended InGaAs nanowire MOSFETs

CMOS photonics technologies based on heterogeneous integration of SiGe/Ge and III-V on Si

An InGaSb p-channel FinFET

Record performance InGaAs homo-junction TFET with superior SS reliability over MOSFET

High-frequency prospects of 2D nanomaterials for flexible nanoelectronics from baseband to sub-THz devices

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Enhancement-mode single-layer CVD MoS2 FET technology for digital electronics

Efficient metallic carbon nanotube removal for highly-scaled technologies

Spintronic majority gates

Spintronic logic circuit and device prototypes utilizing domain walls in ferromagnetic wires with tunnel junction readout

High performance and reliable silicon field emission arrays enabled by silicon nanowire current limiters

Eliminating proximity effects and improving transmission in field emission vacuum microelectronic devices for integrated circuits

A new plasma device operated in liquids for biological applications

Artificially intelligent nanoarrays for disease detection via volatolomics

Flexible graphene hall sensors with high sensitivity

Suspended AlGaN/GaN membrane devices with recessed open gate areas for ultra-low-power air quality monitoring

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Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs

Content Provider	IEEE Xplore Digital Library
Author	Deshpande, V. Djara, V. O'Connor, E. Hashemi, P. Balakrishnan, K. Sousa, M. Caimi, D. Olziersky, A. Czornomaz, L. Fompeyrine, J.
Copyright Year	2015
Description	Author affiliation: IBM Research GmbH Zurich Laboratory, Saumerstrasse 4, CH-8803 Ruschlikon, Switzerland (Deshpande, V.; Djara, V.; O'Connor, E.; Sousa, M.; Caimi, D.; Olziersky, A.; Czornomaz, L.; Fompeyrine, J.) \|\| IBM T.J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, NY 10598 USA (Hashemi, P.; Balakrishnan, K.)
Abstract	We demonstrate, for the first time, scaled hybrid inverters built in a 3D Monolithic (3DM) CMOS process featuring short-channel replacement metal gate (RMG) InGaAs-OI wide-fin/planar nFET top layer and SiGe-OI fin pFET bottom layer. We achieve state-of-the-art device integration, using raised source drain (RSD) on both levels and silicide on bottom pFETs. Bottom SiGe-OI pFETs are scaled down to sub-20 nm gate length (Lg) using a gate first (GF) flow, and top InGaAs nFETs scaled down to sub-50 nm Lg are fabricated using a RMG process. With an optimized thermal budget for the top InGaAs nFETs, we show that the 3D integration scheme does not degrade the performance of the bottom SiGe-OI pFETs. Finally, we demonstrate well-behaved integrated inverters with sub-50 nm Lg down to VDD = 0.25 V.
File Size	1772758
File Format	PDF
ISSN	2156017X
e-ISBN	9781467398947
DOI	10.1109/IEDM.2015.7409658
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Indium gallium arsenide Fabrication Logic gates CMOS integrated circuits Inverters Annealing Three-dimensional displays
Content Type	Text
Resource Type	Article

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