NDLI: A surface-potential based model for GaN HEMTs in RF power amplifier applications

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From the future Si technology perspective: Challenges and opportunities

Energy efficiency enabled by power electronics

Bionano science and technology for innovative medicine

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding

Ultra-thin chip technology for system-in-foil applications

Engineered substrates for future More Moore and More than Moore integrated devices

Extremely-thin-body InGaAs-on-insulator MOSFETs on Si fabricated by direct wafer bonding

Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

Anomalous electron mobility in extremely-thin SOI (ETSOI) diffusion layers with SOI thickness of less than 10 nm and high doping concentration of greater than $1×10^{18}cm^{−3}$

Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX

Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG

An anomalous correlation between gate leakage current and threshold voltage fluctuation in advanced MOSFETs

6Å EOT Si0.45Ge0.55 pMOSFET with optimized reliability (VDD=1V): Meeting the NBTI lifetime target at ultra-thin EOT

An on-chip monitor for statistically significant circuit aging characterization

Product drift from NBTI: Guardbanding, circuit and statistical effects

Recent advances in understanding the bias temperature instability

Modeling the breakdown statistics of gate dielectric stacks including percolation and progressive breakdown

PBTI mechanisms in La containing Hf-based oxides assessed by very Fast IV measurements

Abnormal slow recovery characteristic of La-doped HfSiOx n-MOSFET bias-temperature instability

A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

25nm 64Gb MLC NAND technology and scaling challenges invited paper

Ultimate scalability of TaN metal floating gate with incorporation of high-K blocking dielectrics for Flash memory applications

Highly-scaled 3.6-nm ENT trapping layer MONOS device with good retention and endurance

A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability

Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash

Universal guiding principle for the fabrication of highly scalable MONOS-type memory -atomistic recipes based on designing interface oxygen chemical potential-

Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

Advanced composite high-κ gate stack for mixed anion arsenide-antimonide quantum well transistors

Development of high-k dielectric for antimonides and a sub 350°C III–V pMOSFET outperforming Germanium

Correlation between channel mobility improvements and negative Vth shifts in III–V MISFETs: Dipole fluctuation as new scattering mechanism

Band-engineered Ge-on-Si lasers

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

High-Q torsional mode Si triangular beam resonators encapsulated using SiGe thin film

Fully micromechanical piezo-thermal oscillators

Q-boosted AlN array-composite resonator with Q>10,000

Self-polarized capacitive silicon micromechanical resonators via charge trapping

Sub-100ppb/°C temperature stability in thermally actuated high frequency silicon resonators via degenerate phosphorous doping and bias current optimization

Resonant-body Fin-FETs with sub-nW power consumption

Compact modeling and analysis of coupling noise induced by through-Si-vias in 3-D ICs

Large signal substrate modeling in RF SOI technologies

A surface-potential based model for GaN HEMTs in RF power amplifier applications

FinFET compact modelling for analogue and RF applications

MuGFET carrier mobility and velocity: Impacts of fin aspect ratio, orientation and stress

Phonon-limited mobility and injection velocity in n- and p-doped ultrascaled nanowire field-effect transistors with different crystal orientations

Beating the Nernst limit of 59mV/pH with double-gated nano-scale field-effect transistors and its applications to ultra-sensitive DNA biosensors

Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates

Graphitic interfacial layer to carbon nanotube for low electrical contact resistance

Resistive switching of carbon-based RRAM with CNT electrodes for ultra-dense memory

Magnetic tunnel junction for nonvolatile CMOS logic

Cost-efficient fabrication of UV/Vis nanowire (NW) photodiodes enabled by ZnO/Si radial heterojunction

RF performance of short channel graphene field-effect transistor

Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

CxFET: A novel steep subthreshold swing CMOS featuring a tunnel-injection bipolar transistor and MOSFET device complex

A phase-change via-reconfigurable on-chip inductor

Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel

High performance germanium n-MOSFET with antimony dopant activation beyond $1×10^{20}$ $cm^{−3}$

High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD

Dual Strained Channel co-integration into CMOS, RO and SRAM cells on FDSOI down to 17nm gate length

A solution for an ideal planar multi-gates process for ultimate CMOS?

Diamond-like carbon (DLC) liner with highly compressive stress formed on AlGaN/GaN MOS-HEMTs with in situ silane surface passivation for performance enhancement

Physical origin of pFET threshold voltage modulation by Ge channel ion implantation (GC-I/I)

Preparation of epitaxial HfO2 film (EOT=0.5 nm) on Si substrate using atomic-layer deposition of amorphous film and rapid thermal crystallization (RTC) in an abrupt temperature gradient

A novel multi deposition multi room-temperature annealing technique via Ultraviolet-Ozone to improve high-K/metal (HfZrO/TiN) gate stack integrity for a gate-last process

Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

32nm high-density high-speed T-RAM embedded memory technology

Ultimately scaled 20nm unified-RAM

A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and $10^{16}$ endurance at 85°C

Memory technology trend and future challenges

Switching distributions and write reliability of perpendicular spin torque MRAM

On-axis scheme and novel MTJ structure for sub-30nm Gb density STT-MRAM

Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

Current status and future trends in silicon power devices

AlGaN/GaN transistors for power electronics

Silicon carbide based power devices

Ultra high voltage semiconductor power devices for grid applications

Advanced SiC and GaN power electronics for automotive systems

Advanced power devices for many-core processor power supplies

A leading-edge 0.9µm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling

A 3×3, 5µm pitch, 3-transistor single photon avalanche diode array with integrated 11V bias generation in 90nm CMOS technology

A miniature actively recharged single-photon detector free of afterpulsing effects with 6ns dead time in a 0.18µm CMOS technology

A low dark current and high quantum efficiency monolithic germanium-on-silicon CMOS imager technology for day and night imaging applications

10 µm pixel-to-pixel pitch hybrid backside illuminated AlGaN-on-Si imagers for solar blind EUV radiation detection

Efficiency enhancement and polarization detection capability of photodiode by accumulating local electric field on the metal electrodes

High performance transparent photosensor array utilizing triple oxide semiconductor (HIZO-IZO-HIZO) thin film transistor

Transfer of physically-based models from process to device simulations: Application to advanced Strained Si/SiGe MOSFETs

Simulation study of the on-current improvements in Ge and sGe versus Si and sSi nano-MOSFETs

TCAD: Present state and future challenges

Electrical modulation of ion concentration in dual-gated nanochannels

Theory of workfunction control of silicides by doping for future Si-nano-devices based on fundamental physics of why silicides exist in nature

3D device simulation of work function and interface trap fluctuations on high-κ / metal gate devices

Analysis of pocket profile deactivation and its impact on Vth variation for Laser annealed device using an atomistic kinetic Monte Carlo approach

Prospect of tunneling green transistor for 0.1V CMOS

Performance benchmarks for Si, III–V, TFET, and carbon nanotube FET - re-thinking the technology assessment methodology for complementary logic applications

Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification

A predictive contact reliability model for MEM logic switches

Polymer solid-electrolyte (PSE) switch embedded in 90nm CMOS with forming-free and 10nsec programming for low power, nonvolatile programmable logic (NPL)

Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages

Thruchip interface (TCI) for 3D integration of low-power system

Thermal-aware design of 3D ICs with inter-tier liquid cooling

Device and circuit interactive design and optimization beyond the conventional scaling era

May the fourth (terminal) be with you - circuit design beyond FinFET

Intrinsic variability in nano-CMOS design and beyond

Low-power circuit challenges in cellular/molecular interfaces

Ge MOSFETs performance: Impact of Ge interface passivation

Higher κ metal-gate/high-κ/Ge n-MOSFETs with <1 nm EOT using laser annealing

Prospects for MEM logic switch technology

Record low contact resistivity to n-type Ge for CMOS and memory applications

High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response

9nm half-pitch functional resistive memory cell with <1µA programming current using thermally oxidized sub-stoichiometric WOx film

A forming-free WOx resistive memory using a novel self-aligned field enhancement feature with excellent reliability and scalability

Low power operating bipolar TMO ReRAM for sub 10 nm era

High performance ultra-low energy RRAM with good retention and endurance

Diode-less nano-scale ZrOx/HfOx RRAM device with excellent switching uniformity and reliability for high-density cross-point memory applications

Metal oxide RRAM switching mechanism based on conductive filament microscopic properties

Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance

Spatially-discriminating trap characterization methods for HEMTs and their application to RF-stressed AlGaN/GaN HEMTs

RF power degradation of GaN High Electron Mobility Transistors

A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs

Reliability of enhancement-mode AlGaN/GaN HEMTs under ON-state gate overdrive

Blocking-voltage boosting technology for GaN transistors by widening depletion layer in Si substrates

Normally-off AlGaN/GaN-on-Si MOSHFETs with TaN floating gates and ALD SiO2 tunnel dielectrics

High performance CMOS-compatible super-junction FINFETs for Sub-100V applications

State-of-the-art device in high voltage power ICs with lowest on-state resistance

High performance single-grain Ge TFTs without seed substrate

Ultra-low power TFTs with 10 nm stacked gate insulator fabricated by nitric acid oxidation of Si (NAOS) method

180nm gate length amorphous InGaZnO thin film transistor for high density image sensor applications

Oxide TFT rectifier achieving 13.56-MHz wireless operation with DC output up to 12 V

Very high performance non-volatile memory on flexible plastic substrate

Submicron low-voltage organic transistors and circuits enabled by high-resolution silicon stencil masks

Modeling the switching dynamics of programmable-metallization-cell (PMC) memory and its application as synapse device for a neuromorphic computation system

A model for the RESET operation of electrochemical conducting bridge resistive memory (CB-ReRAM)

The first principle computer simulation and real device characteristics of superlattice phase-change memory

A novel floating body cell memory with a laterally engineered bandgap using a Si-Si:C heterostructure

Investigation of the role of H-related defects in Al2O3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling

3D Monte Carlo simulation of the programming dynamics and their statistical variability in nanoscale charge-trap memories

Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays

Quantitative model for TMR and spin-transfer torque in MTJ devices

Graphene-based fast electronics and optoelectronics

Graphene field-effect transistors based on boron nitride gate dielectrics

Understanding the contact characteristics in single or multi-layer graphene devices: The impact of defects (carbon vacancies) and the asymmetric transportation behavior

Impacts of graphene/SiO2 interaction on FET mobility and Raman spectra in mechanically exfoliated graphene films

RF performance of pre-patterned locally-embedded-back-gate graphene device

Gigahertz ambipolar frequency multiplier based on CVD graphene

Low-resistive and homogenous NiPt-silicide formation using ultra-low temperature annealing with microwave system for 22nm-node CMOS and beyond

Ultra-low series resistance $W/ErSi2/n^{+}-Si$ and $W/Pd2Si/p^{+}-Si$ S/D electrodes for advanced CMOS platform

Contact resistance reduction to FinFET source/drain using dielectric dipole mitigated Schottky barrier height tuning

Atomic-layer-deposited LaAlO3/SrTiO3 all oxide field-effect transistors

Reliable single atom doping and discrete dopant effects on transistor performance

Self-aligned metal source/drain InxGa1−xAs n-MOSFETs using Ni-InGaAs alloy

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

Context dependent effects on LF (1/f) noise in advanced CMOS devices

A $0.039um^{2}$ high performance eDRAM cell based on 32nm High-K/Metal SOI technology

Hysteretic drain-current behavior due to random telegraph noise in Scaled-down FETs with high-κ/metal-gate stacks

Random telegraph noise in 45-nm CMOS: Analysis using an on-chip test and measurement system

Statistical characterization of trap position, energy, amplitude and time constants by RTN measurement of multiple individual traps

Generic learning of TDDB applied to RRAM for improved understanding of conduction and switching mechanism through multiple filaments

Electron trapping effect on the switching behavior of contact RRAM devices through random telegraph noise analysis

The impact of hole-induced electromigration on the cycling endurance of phase change memory

N-doped GeTe as performance booster for embedded Phase-Change Memories

Phase change memory line concept for embedded memory applications

Temperature- and time-dependent conduction controlled by activation energy in PCM

Voltage polarity effects in GST-based phase change memory: Physical origins and implications

Device, circuit and system-level analysis of noise in multi-bit phase-change memory

Three-dimensional $4F^{2}$ ReRAM cell with CMOS logic compatible process

Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application

220GHz fT and 400GHz fmax in 40-nm GaN DH-HEMTs with re-grown ohmic

Advanced gate technologies for state-of-the-art fT in AlGaN/GaN HEMTs

100GHz depletion-mode Ga2O3/GaN single nanowire MOSFET by photo-enhanced chemical oxidation method

High-performance monolithically-integrated E/D mode InAlN/AlN/GaN HEMTs for mixed-signal applications

SiGe HBT technology with fT/fmax of 300GHz/500GHz and 2.0 ps CML gate delay

50-nm E-mode In0.7Ga0.3As PHEMTs on 100-mm InP substrate with fmax > 1 THz

60 nm self-aligned-gate InGaAs HEMTs with record high-frequency characteristics

Novel 140°C hybrid thin film solar cell/transistor technology with 9.6% conversion efficiency and 1.1 $cm^{2}/V-s$ electron mobility for low-temperature substrates

Boosting short circuit current with rationally designed periodic Si nanopillar surface texturing for thin film solar cell

Above-CMOS a-Si and CIGS solar cells for powering autonomous microsystems

Versatile silicon photodiode detector technology for scanning electron microscopy with high-efficiency sub-5 keV electron detection

A CMOS-compatible piezoelectric vibration energy scavenger based on the integration of bulk PZT films on silicon

Integration of organic photovoltaic and thermoelectric hybrid module for energy harvesting applications

Low-field mobility and high-field drift velocity in graphene nanoribbons and graphene bilayers

Full band assessment of phonon-limited mobility in Graphene NanoRibbons

Computational study of graphene nanoribbon FETs for RF applications

High on-off ratio Bilayer Graphene complementary field effect transistors

Multi-scale simulation of partially unzipped CNT hetero-junction Tunneling Field Effect Transistor

GaAs: Gap state passivation at interfaces and surfaces

Test chip fabrication with extreme ultraviolet lithography for high-volume manufacturing

Experimental demonstration of aperiodic patterns of directed self-assembly by block copolymer lithography for random logic circuit layout

A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics

Ultra-high density carbon nanotubes on Al-Cu for advanced vias

High reliability 32 nm Cu/ULK BEOL based on PVD CuMn seed, and its extendibility

Advanced flip-chip package production solution for 40nm/28nm technology nodes

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI

Understanding of short-channel mobility in tri-gate nanowire MOSFETs and enhanced stress memorization technique for performance improvement

Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-к/metal-gate: Effects of hydrogen thermal annealing and nanowire shape

New observations of suppressed randomization in LER/LWR of Si nanowire transistors: Experiments and mechanism analysis

Investigation on TSV impact on 65nm CMOS devices and circuits

A comprehensive breakdown model describing temperature dependent activation energy of low-к/extreme low-к dielectric TDDB

Direct visualization of anomalous-phosphorus diffusion in failure-bit gates of SRAM-load pMOSFETs with high-resolution scanning spreading resistance microscopy

A quantitative inquisition into ESD sensitivity to strain in nanoscale CMOS protection devices

Charged device model (CDM) ESD challenges for laterally diffused nMOS (nLDMOS) silicon controlled rectifier (SCR) devices for high-voltage applications in standard low-voltage CMOS technology

CMOS biosensor platform

A novel smart nanowire biosensor with hybrid sensor/memory/CMOS technology

Design and fabrication of a biomedical Lab-on-Chip system for SNP detection in DNA

A fast and low actuation voltage MEMS switch for mm-wave and its integration

BiCMOS embedded RF-MEMS switch for above 90 GHz applications using backside integration technique

A new charge-trap-engineered memory device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) structure for LTPS-TFT-based applications

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A surface-potential based model for GaN HEMTs in RF power amplifier applications

Content Provider	IEEE Xplore Digital Library
Author	John, D.L. Allerstam, F. Rodle, T. Murad, S.K. Smit, G.D.J.
Copyright Year	2010
Description	Author affiliation: NXP Semiconductors, Central Research, High Tech Campus 4, 5656 AE Eindhoven, The Netherlands (John, D.L.; Smit, G.D.J.) \|\| NXP Semiconductors, PL RF Power and Base Stations, Gerstweg 2, 6534 AE Nijmegen, The Netherlands (Allerstam, F.; Rodle, T.; Murad, S.K.)
Abstract	We present the first surface-potential based compact model for RF GaN HEMTs and benchmark our work against both numerical simulations and device measurements. It is expected that such an approach will be superior to other modeling techniques in terms of scalability and model performance for applications where accurate distortion modeling is of paramount importance.
File Size	169516
File Format	PDF
ISBN	9781442474185
ISSN	2156017X
e-ISBN	9781424474202
e-ISBN	9781424474196
DOI	10.1109/IEDM.2010.5703321
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gallium nitride Integrated circuit modeling MODFETs HEMTs Semiconductor device measurement Numerical models Current measurement
Content Type	Text
Resource Type	Article

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