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Content Provider | IEEE Xplore Digital Library |
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Author | Lau, C.K. Shibata, H. Saitoh, M. Matsuno, T. Samata, S. Itoh, H. Sasaki, H. Hashimoto, K. |
Copyright Year | 1987 |
Description | Author affiliation: Hewlett-Packard Company, Palo Alto, CA, USA (Lau, C.K.) |
Abstract | A novel MOSFET structure is presented in which the source/drain area is minimized by self-aligning to the gate polysilicon. This is achieved by forming a nitride spacer followed by a second field oxidation after gate delineation. A selective silicon growth technique is used to extend the source/drain over the second field oxide for easy contacting. A fully self-aligned contact scheme is employed to conserve overall device area. Besides saving device area and minimizing parasitic capacitance, experimental results at one-micron geometry indicate that other device characteristics are similar to that of the conventional LDD-MOSFET. This device is expected to be scalable well into the submicron regime. |
Starting Page | 358 |
Ending Page | 361 |
File Size | 391867 |
Page Count | 4 |
File Format | |
DOI | 10.1109/IEDM.1987.191431 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1987-12-06 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | MOSFET circuits Oxidation Silicon Parasitic capacitance Implants Protection Etching Very large scale integration Anisotropic magnetoresistance Semiconductor devices |
Content Type | Text |
Resource Type | Article |
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