NDLI: High-density, large scale interconnection for improved VLSI system performance

Content Provider	IEEE Xplore Digital Library
Author	Bertram Jr., W.J.
Copyright Year	1987
Description	Author affiliation: AT&T Bell Laboratories, Murray Hill, New Jersey (Bertram, W.J., Jr.)
Abstract	Improved VLSI chip technology has resulted in vast improvements in the performance of electronic systems. The limitations imposed by conventional chip packaging technology are now a major impediment to further improvement at the system level. Thus we are now placing new requirements on the packaging technologies that are used to interconnect devices and assemble systems. These requirements include the assembly of high pinout (up to 500 I/Os) devices, the ability to sustain synchronous system operation at frequencies up to 100 MHz, the propagation of pulses with risetimes less than 2 ns, and cooling at thermal loads greater than 1 $W/cm^{2}.$ In this paper we describe a packaging technology that overcomes many of the limitations of conventional packaging. This technology, referred to as Advanced VLSI Packaging (AVP), is designed to meet the needs of future VLSI based systems. The substrate for the new technology is a silicon wafer. Power and ground is distributed by means of copper planes on either side of the substrate. Two levels of copper signal conductor are positioned above the power plane using polyimide as the dielectric material. The signal leads are 2 µm thick and a minimum of 10 µm wide. The thickness of the dielectric layer between the power plane and the first signal level and the first and second signal levels is 10 µm and 5 µm, respectively. Devices are attached to the substrate by means of solder, which is applied both to the substrate and to the device chips. The solder technology was choser because it is repairable, provides a low inductance (<0.1 nH) connection between the chip and substrate, and enables I/O pads to be positioned over the area of the chip. The matched thermal expansion coefficient between the substrate and chip results in a mechanically stable solder attachment. With AVP we obtain a very high interconnection density. For a minimum width conductor, the interconnect lines have a resistance of 8 Ω/cm and a capacitance of ∼1 pF/cm. The inductance from the chip to the power, ground or signal conductors is less than 0.1 nH. The conductors can be designed to present a controlled impedance on the order of 50 Ω, or some other desired value. The AVP technology has been demonstrated by means of a prototype vehicle. Three chips from the $WE32100^{®}microprocessor$ chip set: the CPU, MAU and MMU, have been bonded and interconnected on a 1.3 cm by 3.0 cm substrate. The chips are spaced 500 µm apart. The assembly is bonded to a metal heat sink using a compliant adhesive layer to minimize stresses in the silicon substrate. The chip to heat sink thermal resistance for the assembly is 5 °C/Watt (junction to case). A 160 I/O multilayer printed wiring board package has been used to fan out from the edge of the substrate to pins on a 100 mil grid. Wire bonds electrically connect the substrate to the package and provide for chip backside grounding. A protective cover completes the package assembly. Significant improvements in system performance can be achieved using AVP multichip packaging technology. Compared with conventional packaging, a factor of 3 improvement in system operating frequency is expected when ICs are designed specifically for use with AVP. System size can be reduced by a factor of 7 and power dissipation reduced by 30%. The emphasis in this paper will be on the technological aspects of the packaging system: the multilevel, high conductivity metallization system; characteristics of interlevel dielectrics; via formation and filling; and basic reliability studies.
Starting Page	100
Ending Page	103
File Size	439228
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1987.191359
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1987-12-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Very large scale integration System performance Dielectric substrates Conductors Electronics packaging Impedance Assembly systems Frequency Silicon
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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