NDLI: 180V analog-compatible, high-speed logic utilizing semi-well isolation technology

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Plenary session—Invited papers

Microelectronics: End of the beginning or beginning of the end?

Trends in megabit DRAMs

GaAs IC technology - Impact on the semiconductor industry

Session 2 Detectors, sensors and displays — High density image sensors

Charge coupled devices for X-ray imaging

A design consideration on P-well structure for solid-state image sensors

The pinned photodiode for an interline-transfer CCD image sensor

Elimination of fixed pattern noise in super-8 format CCD image sensor by the use of epitaxial wafers

Solid state color imager with buried oxide wall fabricated by low pressure selective epitaxy

The Accordion imager: An ultra high density frame transfer CCD

A single chip 1/2" frame transfer CCD color image sensor

Session 3 Integrated circuits — MOS process technologies

Reliability in MOS integrated circuits

A double layer metal CHMOS III technology

Hi-CMOS III technology

Twin tub III - A third generation CMOS technology

A new full CMOS SRAM cell structure

A manufacturable 1.2 um double poly, double level metal CMOS process for a one-megabit DRAM

NMOS Process integration for a 1m word × 1 bit DRAM

Session 4 Solid state devices — Hot carriers in MOSFETs

Hot carriers in small geometry CMOS

A study of avalanche breakdown in scaled n-MOSFETs

Enhancement of hot-electron currents in graded-gate-oxide (GGO)-MOSFETs

Low voltage hot-electron effects in short channel MOSFETs

A comparative study of tunneling, substrate hot-electron and channel hot-electron injection induced degradation in thin-gate MOSFET's

Hot carrier effects in MOS transistors

Hot carrier degradation mechanism in n-MOSFETS

Session 5 Device technology — Interconnects

Silicide for contacts and interconnects

Layered and homogeneous films of aluminum and aluminum/silicon with titanium, zirconium, and tungsten for multilevel interconnects

A new device interconnect scheme for sub-micron VLSI

Tungsten gate technology using wet hydrogen oxidation

Multilevel interconnection technology

Self-aligned titanium silicidation of submicron MOS devices by rapid lamp annealing

Mo/TiW contact for VLSI applications

Ion implanted double level metal process

Session 6 Device technology — Insulators

A new SiO2growth by Fluorine-enhanced thermal oxidation

Electric field and current dependence of SiO2intrinsic breakdown

Characterization of very thin gate-oxide MOS devices

Studies of trapping and conduction in ultrathin SiO2gate insulators

Oxidized silicon nitride films in thin insulator MIS structures

Ultrathin thermal silicon nitride and nitroxide gate insulators for VLSI

Electrical and structural characteristics of thin nitrided gate oxides prepared by rapid thermal nitridation

Stacked SiO2/Si3N4/SiO2dielectric layer for reliable memory capacitor

Session 7 Quantum electronics and compound semiconductor devices — High speed compound semiconductor devices and device physics

Phase nonlinearity of buried-layer GaAs MESFET's

Low frequency oscillations in undoped GaAs as a probe to deep level parameters

Trapezoidal-groove Schottky-gate vertical channel GaAs FET (GaAs static induction transistor)

InP high power MISFET

A new self-align technology for low noise GaAs MESFET's —Sidewall-assisted pattern inversion technology

GaAs/AlGaAs heterojunction bipolar transistors with very low base sheet resistance

New lateral GaAs transistor

Session 8 Detectors, sensors and displays — Technologies for integrated sensors

Integrating sensors and electronics—New challenges for silicon

Fabrication technology for a chronic in-vivo pressure sensor

Integrated resonant-microbridge vapor sensor

Monolithic silicon fabrication technology for flexible circuit and sensor arrays

A mutual capacitive normal-and shear-sensitive tactile sensor

Planar processed polysilicon sealed cavities for pressure transducer arrays

Session 9 Integrated circuits — Random access memories

Polysilicon transistors in VLSI MOS memories

Scaling consideration and dielectric breakdown improvement of corrugated capacitor cell (CCC) for future DRAM

Buried isolation capacitor (BIC) cell for megabit MOS dynamic RAM

An isolation-merged vertical capacitor cell for large capacity DRAM

A folded capacitor cell (F.C.C.) for future megabit DRAMs

Trench capacitor leakage in Mbit DRAMs

A new soft error mechanism of dynamic memory with grounded cell plate

Session 10 Solid state devices — High voltage integrated circuits and composite devices

Comparison of high voltage devices for power integrated circuits

New high voltage IC technology

850V NMOS driver with active outputs

Recent advances in discrete power transistors

Insulated gate transistor modeling and optimization

Comparison of n and p channel IGTs

MOS Controlled thyristors (MCT's)

Session 11 Integrated circuits — Analysis and characterization of integrated CMOS structures

Computer-aids for analysis and scaling of extrinsic devices

Analysis of latchup susceptibility in CMOS circuits

Recent developments in CMOS latchup

An analytical model for intrinsic capacitances of short-channel MOSFETs

Performance of CMOS circuits with LDD-type NMOSFET's for high density static RAM's

Submicron CCD memory structures fabricated by electron-beam lithography

Session 12 Electron tubes — Cathode and electron guns — Design and performance

High current density cathodes - An update

Dispenser cathode life prediction model

An improved dispenser cathode

A pressed multi-layer Nickel matrix cathode

High reliability TWTs for satellite applications

A powerful quality assurance technique for dispenser cathodes and electron guns

Session 13 Quantum electronics and compound semiconductor devices — III-V heterostructure devices for high speed ICs

Material and device considerations for HEMT LSI

A GaAs 12 × 12 bit expandable parallel multiplier LSI using sidewall-assisted closely-spaced electrode technology

Pulse doped MODFET's

GaAs/AlGaAs double heterostructure high electron mobility transistors

High transconductance InAlAs/InGaAs double heterostructure MESFETs with in-situ aluminum oxide gate barrier

Microwave characterization of very high transconductance MODFET

Two-dimensional transient simulation of the high electron mobility transistor

Session 14 Detectors, sensors and displays — Infrared detectors

Recent advances in platinum silicide infrared focal plane arrays

Monolithic intrinsic NMOS HgCdTe IRCCDs with on-chip signal processing

Development of an improved 16 × 64 InSb CID array

Fully-integrated ZnO on silicon pyroelectric infrared detector array

Growth and characterization of as grown p-n junctions fabricated in multilayer liquid phase epitaxial (Hg, Cd)Te

Surface leakage current mechanisms in HgCdTe gate controlled photodiodes

Hg diffused Hg1-xCdxTe photodiodes for LWIR direct detection applications

Session 15 Device technology — Advanced CMOS technology

Characterization and modeling of a latchup-free 1-µm CMOS technology

Latchup free CMOS using guarded Schottky barrier PMOS

A new method for preventing CMOS latch-up

Reduced $n^{+}/p^{+}-spacing$ with high latchup hardness in self-aligned double well CMOS technology

Deep-submicron MOSFET characteristics with 5 nm gate oxide

A fine-line CMOS technology that uses $p^{+}polysilicon/silicide$ gates for NMOS and PMOS devices

High performance subhalf-micrometer P-channel transistors for CMOS VLSI

Session 16 Solid state devices — Thyristors and high frequency power MOSFETs

Turn-on reliability breakthrough in light triggered thyristors

A new triggering mode for light-triggered thyristors

A very high sensitivity and very high speed light triggered and light quenched static induction thyristor (LTQSIThy)

A highly interdigitated GTO power switch with recessed gate structure

Numerical simulation of the GTO thyristor

A 900 MHz 100 W VD-MOSFET with silicide gate self-aligned channel

VHF High power $VD^{2}MOSFET$

Session 17 Integrated circuits — Non-volatile memory technology

Technology requirements for mega bit CMOS EPROMs

A high performance CMOS process for the next generation EPROM

A new flash $E^{2}PROM$ cell using triple polysilicon technology

Design of an $E^{2}PROM$ memory cell less than 100 square microns using 1 micron technology

A shielded substrate injector MOS (SSIMOS) EEPROM cell

Conduction in thermal oxides grown on polysilicon and its influence on floating gate EEPROM degradation

Endurance model for textured-poly floating gate memories

Session 18 Electron tubes — Travelling wave tubes

Slow-wave structures in microwave tubes

A highly efficient, linear, high power X-band coupled cavity TWT for airborne radar

Recent progress in millimeter-wave tunneladder TWTs

750 W Helix TWT for 14 GHz earth stations

Recent advances in an EHF helix TWT

44 GHz Helix TWTs for satellite communication systems

Session 19 Quantum electronics and compound semiconductor devices — Lasers and heterostructures

Frequency control of semiconductor lasers

Single longitudinal mode distributed feedback double channel planar buried heterostructure 1.55µm InGaAsP/InP lasers

Improved high power twin channel laser with blocking layer

Monolithic integration of a quantum-well laser and a driver circuit on a GaAs substrate

InGaAs/GaAs, strained-layer superlattice (SLS), junction photodetectors, LED's, injection laser's, and FET's for optoelectronic IC applications

AlAs/GaAs superlattice barrier unipolar diode structure

Characterization of double heterojunction GaAs/AlGaAs hot electron transistors

Session 20 Multi-layer interconnection technology

Session 21 Computer automated manufacturing of integrated circuits

Session 22 High-speed monolithic digital and analog devices

Session 23 Future directions of power tube research and development

Session 24 Next generation VLSI power supply standards (5V →?)

Session 25 Detectors, sensors and displays — New sensor technologies and characterization methods

High-gain photodetectors in thin-film transistors fabricated from laser-crystallized silicon on fused silica

A half inch size CCD image sensor overlaid with a hydrogenated amorphous silicon

Characterization of dark current in CCD imagers

Electron-beam induced current measurement of HgCdTe heterojunction infrared detectors

A.C. Characterization and modeling of lateral bipolar magnetotransistors

Sensitivity and noise of a lateral bipolar magnetotransistor in CMOS technology

Session 26 Device technology — Advanced isolation technologies

Trench isolation prospects for application in CMOS VLSI

A new trench isolation technology as a replacement of LOCOS

New techniques for elimination of the bird's head and bird's beak

Defect generation in trench isolation

A fully scaled submicron direct write E-beam CMOS technology for ULSI digital applications

Application of selective silicon epitaxial growth for CMOS technology

Session 27 Solid state devices — Advanced MOS devices and models

Cryogenic behavior of scaled CMOS devices

1.5 µm Gate CMOS operated at 77 K

Effects of surface roughness in inversion layer transport

A new p-channel MOSFET structure with Schottky-clamped source and drain

Scaling of compensated MOSFETs towards submicron dimensions

A small-signal high-frequency model for the four-terminal intrinsic MOSFET valid in all regions of operation

Two-dimensional MOSFET simulation with energy transport phenomena

Session 28 Device technology — Advanced technologies

Process considerations in restructurable VLSI for wafer-scale integration

Silicon nitride films by plasma-CVD from SiH4-N2and SiF4-N2-H2gas mixtures

Elevated source/drain MOSFET

Multiple self-alignment MOS technology (MUSA/MOST)

N- and p-well process compatibility in a 1µm-CMOS technology

A highly reliable N-MOS process for one megabit dynamic random access memory

Session 29 Electron tubes — Klystrons, collectors, and computations

Development of 2 GHz, 1 MW klystron for plasma heating

A wideband 3 MW peak power S-band klystron

KlystrodeTMupdate

An experimental test station for multistage depressed collectors

Large scale simulation of electron devices

Computations of VSWR and mode conversion for complex gyrotron window geometries

A numerical method for predicting brillouin plots of coupled cavity circuits

Session 30 Integrated circuits — Bipolar and buried-layer MOS structures

A 1.6 GHz low power silicon dual modulus prescaler IC

An 80 ps ECL circuit with high current density transistor

A 2 micron high performance bipolar 64K ECL static RAM technology with 200 square microns contactless memory cell

Performance and structures of scaled-down bipolar devices merged with CMOSFETs

180V analog-compatible, high-speed logic utilizing semi-well isolation technology

SOI-CMOS 4K SRAM with high dose oxygen implanted substrate

A P-type buried layer for protection against soft errors in high density CMOS static RAMs

Session 31 Quantum electronics and compound semiconductor devices — Photodetectors

Ultra high speed photodetectors

Fast InGaAs photoconductive detectors with speed enhanced by Berylium ion bombardment

Ion implanted lateral In.2Ga.8As/GaAs strained-layer superlattice photodetector

New pseudo-quaternary GaInAsP semiconductors: A high speed "High-low" avalanche photodiode with Ga0.47In0.53As/InP graded gap superlattice

Fully optical and electrically interfaced, monolithic 1 × 12 array of In0.53Ga0.47As/InP p-i-n photodiodes

GaInAs, AlInAs Schottky barrier diodes and GaInAs/AlInAs heterojunction diode as internal photoemission detectors

A high speed, low voltage silicon photodiode with buried isolation region

Session 32 Device technology — Advanced bipolar technology

Conduction mechanisms of polysilicon emitters with thin interfacial oxide layers

SIPOS Heterojunction contacts to silicon

A silicon bipolar transistor with a hydrogenated amorphous emitter

Self-aligned bipolar transistors with enhanced efficiency polysilicon emitters

New self-aligned complementary bipolar transistors using selective-oxidation mask

Modeling of polysilicon dopant diffusion for shallow-junction bipolar technology

2 Micron merged bipolar-CMOS technology

Session 33 Solid state devices — Lightly-doped drain MOSFETs

State-of-the-art of MOS modeling

Optimization of lightly doped drain MOSFETs using a new quasiballistic simulation tool

Hot carrier degradation modes and optimization of LDD MOSFETs

Effects of field boron dose on substrate current in narrow channel LDD MOSFETs

Characterization of As-P double diffused drain structure

Mechanism of hot electron induced degradation in LDD NMOS-FET

Session 34 Device technology — SOI and 3-D technologies

Fabrication of high speed 1 micron FIPOS/CMOS

Advances in oxidized porous silicon for SOI

Electrical characterisation of oxygen implanted silicon substrates

Device performances of a submicron SOI technology

Merged CMOS/bipolar technologies and microwave MESFETs utilizing zone-melting-recrystallized SOI films

Promissing new fabrication process developed for stacked LSI's

Session 35 Electron tubes — Fast wave tubes

Survey of physics research in microwave devices

A 60 GHz, 200 kW CW gyrotron with high output mode purity

A 100 GHz, 500 kW gyrotron oscillator

Design considerations for a 100 kW CW, 140 GHz gyrotron oscillator

Performance of a three-cavity gyroklystron

Fourth harmonic gyromagnetron development

Peniotron amplifier results

Thick selective tungsten for VLSI: Selectivity enhancement considerations

Complementary p-MODFET and n-HB MESFET (Al,Ga)As FET's

Characteristics of GaAs/AlGaAs MODFETs grown directly on

Realization of sub-10 picosecond switching times in selectively doped (Al,Ga)As/GaAs heterostructure transistors

Ultra-shallow high concentration B profiles for VLSI

Non-latch-up 1200V 75A bipolar-mode MOSFET with large ASO

Fast-response PIN/Preamplifier photoreceiver monolithically integrated on a GaAs substrate

Microwave performance of GaAs/(Ga,Al)As heterojunction bipolar transistors

Modification of silicon electronic band structure using submicron period gate electrodes

A Si permeable base transistor by metal/Semiconductor hetero-epitaxy

A fully self-aligned stacked CMOS 64K SRAM

Field theory analysis of the pill box window

1983 International Electron Devices Meeting

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180V analog-compatible, high-speed logic utilizing semi-well isolation technology

Content Provider	IEEE Xplore Digital Library
Author	Okabe, T. Kimura, M. Shimizu, I. Nagai, Y. Nagata, M.
Copyright Year	1984
Description	Author affiliation: Hitachi Ltd., Kokubunji, Tokyo (Okabe, T.)
Abstract	A new high-voltage LSI fabrication technique realizing a push-pull output circuit with compact low-power and high-speed logic has been developed. The unique feature of this technique is that it provides compatibility for high-voltage devices with low-power IIL and high-speed Complementary Schottky Transistor Logic(CSTL) on a single chip by using an improved Semi-Well Isolation structure. As a result, logic circuits having minimum propagation delay times of 35ns/gate for IIL and 2ns/gate for CSTL were realized on the same chip with 180V devices.
Starting Page	698
Ending Page	701
File Size	355385
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1984.190819
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1984-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Isolation technology Logic devices Logic circuits Epitaxial layers Large scale integration Fabrication Plasma displays Substrates Electric variables Conductivity
Content Type	Text
Resource Type	Article

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