NDLI: Comparison of latch-up in p- and n-well CMOS circuits

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Comparison of latch-up in p- and n-well CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Takacs, D. Harter, J. Jacobs, E.P. Werner, C. Schwabe, U. Winnerl, J. Lange, E.
Copyright Year	1983
Description	Author affiliation: Siemens AG, Munich, FRG (Takacs, D.)
Abstract	The latch-up hardness of p- and n-well CMOS concepts is compared for processes with and without epitaxial layer using electrical and laser-scanning measurements as well as theoretical calculations. It is shown that latch-up hardness does not primarily depend on the parasitic bipolar gain products, which are different for the two concepts, but rather on the shunt resistors in the well and in the substrate. This leads to equal latch-up hardness for n- and p-well concepts without epitaxy. With epitaxy latch-up hardness is strongly increased and is in the case of a p-well by a factor of 5 higher compared with the n-well concept. This is due to the enhanced diffusion of Boron from the $p^{+}-substrate$ in the epitaxial layer.
Starting Page	159
Ending Page	163
File Size	385388
Page Count	5
File Format	PDF
DOI	10.1109/IEDM.1983.190466
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1983-12-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Electric variables measurement CMOS process Substrates Voltage Epitaxial layers Laser theory Epitaxial growth Very large scale integration MOSFETs
Content Type	Text
Resource Type	Article

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