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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shida, A. Kagamihara, M. Komatsu, M. Kumagai, K. Hirata, M. |
| Copyright Year | 1991 |
| Description | Author affiliation: NEC Corp., Kanagawa, Japan (Shida, A.; Kagamihara, M.; Komatsu, M.; Kumagai, K.; Hirata, M.) |
| Abstract | A VLSI technology suitable for low-voltage BiNMOS logic has been developed. A BiNMOS device structure, N substrate based emitter-followed CMOS (NECMOS), is proposed. NECMOS has a simple structure using a substrate NPN (S-NPN) transistor which does not need buried layers. This use of an N substrate and a thin epitaxial layer is capable of realizing low collector resistance for S-NPN. A polysilicon emitter type S-NPN transistor, with a maximum cutoff frequency of 9 GHz, has been integrated into a 0.8 mu m CMOS structure with three additional masks. The fan-out coefficient of the propagation delay time for a BiNMOS 2-NAND gate is 1/2.4 of that for a CMOS 2-NAND gate under 3.3 V operation.< |
| Starting Page | 93 |
| Ending Page | 96 |
| File Size | 309492 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780302435 |
| ISSN | 01631918 |
| DOI | 10.1109/IEDM.1991.235416 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-12-08 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Epitaxial layers Substrates Logic devices CMOS logic circuits BiCMOS integrated circuits Impurities Boron Large scale integration National electric code Very large scale integration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering |
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