NDLI: A new super high speed ECL compatible $I^{2}L$ technology

Content Provider	IEEE Xplore Digital Library
Author	Kanzaki, K. Taguchi, M. Sasaki, G. Furukawa, A. Aoki, K. Tokumaru, Y. Nakai, M. Ikeda, M.
Copyright Year	1979
Description	Author affiliation: Toshiba Corporation (Kanzaki, K.)
Abstract	A new technology for realizing high performance $I^{2}L$ and high speed ECL circuits on a same chip is described. The key to such a technology is graft base structure having respectively optimized impurity profiles for $I^{2}L$ gates and linear transistors. All of base regions $(I^{2}L;$ $P^{+},$ $P^{--},$ a linear transistor; $P^{++},$ $P^{-})$ are formed in different doping steps, followed by only one $n^{+}diffusion$ for $I^{2}L$ collector and the linear transistor's emitter. $I^{2}L$ $P^{--}intrinsic$ base region formed by high energy ion implantation has a smaller Gummel number and a deeper junction depth than in the linear transistor. $I^{2}L$ $P^{+}extrinsic$ base region is deeper in junction depth than linear $P^{++}base$ region. A high speed $I^{2}L$ gate with upward current gain of 30 and 7 ns minimum delay could be compatible with a linear transistor having downward current gain of 80, BVCEOof 18 V and 4 GHz maximum cut off frequency. Futhermore, an ECL divider has successfully operated at frequencies up to 1.4 GHz.
Starting Page	328
Ending Page	331
File Size	376045
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1979.189616
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-12-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Doping Frequency Logic Large scale integration Inverters Semiconductor devices Laboratories Semiconductor impurities Delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A high speed $I^{2}L$ compatible with high voltage analog devices

Static induction transistor logic compatible with 1GHz ECL circuits

Leading-zero anticipatory logic for high-speed floating point addition

Advances in high speed ECL technology and interconnection techniques

A new high speed I/sup 2/L structure

A high-voltage analog-compatible $I^{2}L$ process

Up-diffused $I^{2}L,$ a high speed bipolar LSI process

Integrated 84ps ECL with $I^{2}L$

$I^{2}L,$ On-Chip Compatible with High Voltage Analog Functions, Obtained by Selective Epi-Doping

A new super high speed ECL compatible $I^{2}L$ technology

Similar Documents

A high speed $I^{2}L$ compatible with high voltage analog devices

Static induction transistor logic compatible with 1GHz ECL circuits

Leading-zero anticipatory logic for high-speed floating point addition

Advances in high speed ECL technology and interconnection techniques

A new high speed I/sup 2/L structure

A high-voltage analog-compatible $I^{2}L$ process

Up-diffused $I^{2}L,$ a high speed bipolar LSI process

Integrated 84ps ECL with $I^{2}L$

$I^{2}L,$ On-Chip Compatible with High Voltage Analog Functions, Obtained by Selective Epi-Doping

A new super high speed ECL compatible $I^{2}L$ technology