NDLI: A high density overlapping gate charge coupled device array

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A high density overlapping gate charge coupled device array

Content Provider	IEEE Xplore Digital Library
Author	Bower, R.W. Zimmerman, T.A. Mohsen, A.M.
Copyright Year	1973
Description	Author affiliation: TRW Systems Group, Redondo Beach, California (Bower, R.W.)
Abstract	In this talk a technique for constructing a high density overlapping gate charge coupled device array is described and experimental verification of the concept is presented. The technique involves forming an asymmetrical well within each gate region. A bit density advantage of nearly four to one compared with a standard poly-silicon overlapping gate structure is achieved; this comparison is based upon serpentine arrays using identical mask design rules in each case. A density greater $than6\times10^\{6\}bits/inch^{2}results$ using a minimum geometry length of five microns. The array structure will be described and array characteristics will be given and compared to standard overlapping gate arrays.
Starting Page	30
Ending Page	32
File Size	326685
Page Count	3
File Format	PDF
DOI	10.1109/IEDM.1973.188640
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1973-12-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Charge-coupled image sensors Electrodes Phased arrays Charge coupled devices Geometry Capacitance-voltage characteristics Clocks Couplings Insulation Telephony
Content Type	Text
Resource Type	Article

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