NDLI: 50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

Content Provider	IEEE Xplore Digital Library
Author	Kim, Y.W. Oh, C.B. Ko, Y.G. Lee, K.T. Ahn, J.H. Park, T.S. Kang, H.S. Lee, D.H. Jung, M.K. Yu, H.J. Jung, K.S. Liu, S.H. Oh, B.J. Kim, K.S. Lee, N.I. Park, M.H. Bae, G.J. Lee, S.G. Song, W.S. Wee, Y.G. Jeon, C.H. Suh, K.P.
Copyright Year	2002
Description	Author affiliation: Syst. LSI Div., Samsung Electron., South Korea (Kim, Y.W.; Oh, C.B.; Ko, Y.G.; Lee, K.T.; Ahn, J.H.; Park, T.S.; Kang, H.S.; Lee, D.H.; Jung, M.K.; Yu, H.J.; Jung, K.S.; Liu, S.H.; Oh, B.J.; Kim, K.S.; Lee, N.I.; Park, M.H.; Bae, G.J.; Lee, S.G.; Song, W.S.; Wee, Y.G.; Jeon, C.H.; Suh, K.P.)
Abstract	A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.
Sponsorship	Electron. Devices Soc. IEEE
Starting Page	69
Ending Page	72
File Size	356785
Page Count	4
File Format	PDF
ISBN	0780374622
DOI	10.1109/IEDM.2002.1175781
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Logic devices MOS devices High K dielectric materials System-on-a-chip High-K gate dielectrics CMOS logic circuits CMOS technology Dielectric devices Portfolios
Content Type	Text
Resource Type	Article

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