NDLI: Tunable work function dual metal gate technology for bulk and non-bulk CMOS

Content Provider	IEEE Xplore Digital Library
Author	JaeHoon Lee Huicai Zhong You-Seok Suh Heuss, G. Gurganus, J. Bei Chen Misra, V.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., North Carolina State Univ., Raleigh, NC, USA (JaeHoon Lee; Huicai Zhong; You-Seok Suh; Heuss, G.; Gurganus, J.; Bei Chen; Misra, V.)
Abstract	This paper describes a metal gate process, which provides tunable work function values and ease of integration for dual metal gate process flow. Vertical stacks of Ru and Ta layers were subjected to high temperature anneals to promote intermixing which resulted in /spl phi//sub m/ tuning. It was found that Ru/Ta stacks provided up to 0.4 eV reduction in /spl phi//sub m/ compared to Ru. To increase this change, stacks of Ru/sub 50/Ta/sub 50//Ru were also evaluated and nearly a 0.8 eV change in /spl phi//sub m/ was observed between Ru/sub 50/Ta/sub 50//Ru and Ru/sub 50/Ta/sub 50/ electrodes.
Sponsorship	Electron. Devices Soc. IEEE
Starting Page	359
Ending Page	362
File Size	244611
Page Count	4
File Format	PDF
ISBN	0780374622
DOI	10.1109/IEDM.2002.1175852
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Channel bank filters Annealing Electrodes Capacitance-voltage characteristics Temperature MOS capacitors Fluctuations Fabrication Stability
Content Type	Text
Resource Type	Article

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