NDLI: ASIC package to board BGA discontinuity characterization in >10Gbps SerDes links

Content Provider	IEEE Xplore Digital Library
Author	Lim, J. Ji Zhang Wei Yao Tseng, K. Qiu, K. Brooks, R. Jun Fan
Copyright Year	2013
Description	Author affiliation: Cisco Syst. Inc., San Jose, CA, USA (Lim, J.; Ji Zhang; Wei Yao; Tseng, K.; Qiu, K.; Brooks, R.) \|\| Missouri Univ. of Sci. & Technol., Rolla, MO, USA (Jun Fan)
Abstract	High performance ASIC packages are typically mounted on the PCB using BGA solder ball technology; ASIC package to board BGA transition creates impedance discontinuity in the multi-gigabit signaling channel. It is important to understand and model this discontinuity accurately to improve end to end channel design in system level. Usually when the channel is simulated, instead of modeling the package with the PCB together in one model, also known as one piece model, separate models are built for package and PCB and the individual models are then cascaded using the circuit simulator. If the models are not setup correctly in the field solvers, i.e. port definition, it may not capture the transition behavior correctly and hence makes the cascaded channel model results differ from one piece model and/or real channel measurement. This paper discusses the detailed modeling of the BGA solder ball transition to enable the model concatenation method suitable to be used for system level channel prediction. The package only model, board only model and one piece model were simulated upto 20GHz using either lump port or wave port setup in ANSYS HFSS field solver. The cascaded model with wave port connection and one piece model are found well matched. The lump-port connection can introduce extra parasitic inductance at the BGA connection point and hence is not recommended. Hardware (package and PCB test samples) have been built to characterize this transition behavior for model to hardware correlation. The FSA (Feature Selected Validation) method is used to quantify the correlation results, both insertion loss and return loss are compared to gain confidence on the simulation results and high-speed channel prediction.
Starting Page	569
Ending Page	574
File Size	1238987
Page Count	6
File Format	PDF
ISBN	9781479904082
ISSN	21581118
e-ISBN	9781479904105
DOI	10.1109/ISEMC.2013.6670477
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Integrated circuit modeling Correlation Impedance Insertion loss Analytical models Inductance
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering

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