NDLI: Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits

Content Provider	IEEE Xplore Digital Library
Author	Iokibe, K. Amano, T. Okamoto, K. Toyota, Y. Watanabe, T.
Copyright Year	2013
Description	Author affiliation: Ind. Technol. Center of Okayama Prefecture, Okayama, Japan (Watanabe, T.) \|\| Grad. Sch. of Natural Sci. & Technol., Okayama Univ., Okayama, Japan (Iokibe, K.; Amano, T.; Okamoto, K.; Toyota, Y.)
Abstract	The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.
Starting Page	834
Ending Page	839
File Size	1470895
Page Count	6
File Format	PDF
ISBN	9781479904082
ISSN	21581118
e-ISBN	9781479904105
DOI	10.1109/ISEMC.2013.6670526
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryptography Bandwidth High definition video Time-frequency analysis Time measurement Couplings
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering

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