NDLI: ASIC package design optimization for 10 Gbps and above backplane serdes links

Content Provider	IEEE Xplore Digital Library
Author	Lim, J. Kai Soon Chow Ji Zhang Jianmin Zhang Qiu, K. Brooks, R.
Copyright Year	2012
Description	Author affiliation: Missouri University of Science and Technology 1870 Miner Circle, Rolla, MO 65409 (Ji Zhang) \|\| Cisco Systems, Inc 170 West Tasman Dr, San Jose, CA 95134 (Lim, J.; Kai Soon Chow; Jianmin Zhang; Qiu, K.; Brooks, R.)
Abstract	This paper discussed the package selection and BGA signal pin assignment consideration for high-end ASIC design with over 400 SerDes (Serializer Deserializer) pairs for >10Gbps backplane interface. The ASIC package is using advanced high-performance organic build-up (BU) materials like GX13, GZ41 and thinner core in the stack-up to help reduce the package loss and improve the signal transmission on the highspeed SerDes links. For return loss and insertion loss studies, the main objectives are to investigate the core thickness, BU material properties, and routing configurations impact on the differential signalling. The design suggestions are then made at each area for performance and cost optimization. For crosstalk studies, various pin-out patterns for transmit to transmit or receive to receive signals, and transmit to receive signals, have been designed and studied to investigate signal coupling and PCB escape routing requirements. Both frequency and time domain simulations are performed to compare the signal isolation performance. The most optimized pin-out is then selected to achieve the overall required system performance. Lastly, various package substrate samples with different BU materials, core thicknesses and crosstalk structures are manufactured to validate package design performance using probe station technique.
Starting Page	199
Ending Page	204
File Size	1087438
Page Count	6
File Format	PDF
ISBN	9781467320610
ISSN	21581118
e-ISBN	9781467320603
DOI	10.1109/ISEMC.2012.6351784
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dielectric losses Materials Crosstalk Couplings Insertion loss Routing Loss measurement
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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