NDLI: Evaluating thread level parallelism based on optimum cache architecture

Content Provider	IEEE Xplore Digital Library
Author	Alipour, M. Khorramshahi, B.A. Karimi, F. Mirzaei, Z. Vaghari, A.
Copyright Year	2012
Description	Author affiliation: Allameh Rafiei Higher Education Institute of Qazvin, Iran (Alipour, M.; Khorramshahi, B.A.; Karimi, F.; Mirzaei, Z.; Vaghari, A.)
Abstract	By scaling down the feature size and emersion of multi-cores that are usually multi-thread processors, the performance requirements almost guaranteed. Despite the ubiquity of multi-cores, it is as important as ever to deliver high single-thread performance. Multithreaded processors, by simultaneously using both the thread-level parallelism and the instruction-level parallelism of applications, achieve larger instruction per cycle rate than single-thread processors. In the recent multi-core multi-thread systems, the performance and power consumption is severely related to the average memory access time and its power consumption. This makes the cache as a major and important part in designing multi-thread multi-core embedded processor architectures. In this paper we perform a comprehensive design space exploration to find cache sizes that create the best tradeoffs between performance, power, and area of the processor. Finally we run multiple threads on the proposed optimum architecture to find out the maximum thread level parallelism based on performance per power and area efficient uni-thread architecture.
Starting Page	48
Ending Page	53
File Size	374805
Page Count	6
File Format	PDF
ISBN	9781467330329
e-ISBN	9781467330336
DOI	10.1109/ISCAIE.2012.6482067
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-03
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Multithreading Instruction sets Embedded processor Performance per power Computer architecture Hardware Multithread architecture Space exploration MIPS Cache Hyper threading
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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