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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dongdong Chen Yu Zhang Li Chen Teng, D. Wahid, K. Seok-Bum Ko |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Saskatchewan Univ., Saskatoon, SK (Dongdong Chen; Yu Zhang; Li Chen; Teng, D.; Wahid, K.; Seok-Bum Ko) |
| Abstract | This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal antilogarithmic converter. A linear approximation algorithm is proposed and simulated in MATLAB models. The maximum absolute error of the proposed decimal antilogarithmic converter is in the range of -0.000999 les $E_{absolute}$ les 0.000857 and the maximum percent error is in the range of -0.000715 les $E_{percent}$ les 0.000691. The proposed decimal-to-decimal antilogarithmic converter is modeled in VHDL and implemented using a Xilinx Virtex-II Pro P30 FPGA device. The converter is implemented using combinational logic only and it computes decimal antilogarithms results in a single clock cycle, running at 53.1 MHz. |
| Starting Page | 001223 |
| Ending Page | 001226 |
| File Size | 127585 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424416424 |
| ISSN | 08407789 |
| DOI | 10.1109/CCECE.2008.4564734 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-04 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Approximation algorithms Signal processing algorithms Linear approximation Field programmable gate arrays Mathematical model Digital arithmetic Hardware Floating-point arithmetic Computational modeling MATLAB FPGA Decimal-to-decimal Antilogarithmic Converter |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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