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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tuhin, M. Norvell, T.S. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, NL (Tuhin, M.) |
| Abstract | In this paper a novel approach for compiling parallel applications to a target coarse-grained reconfigurable architecture (CGRA) is presented. We have given a formal definition of the compilation problem for the CGRA. The application will be written in HARPO/L, a parallel object oriented language suitable for hardware. HARPO/L is first compiled to a data flow graph (DFG) representation. The remaining compilation steps are a combination of three tasks: scheduling, placement and routing. For compiling cyclic portions of the application, we have adapted a modulo scheduling algorithm: modulo scheduling with integrated register spilling. For scheduling, the nodes of the DFG are ordered using the hypernode reduction modulo scheduling (HRMS) method. The placement and routing is done using the neighborhood relations of the PEs. |
| Starting Page | 001723 |
| Ending Page | 001728 |
| File Size | 136892 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424416424 |
| ISSN | 08407789 |
| DOI | 10.1109/CCECE.2008.4564838 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-04 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Reconfigurable architectures Routing Application software Processor scheduling Registers Hardware Field programmable gate arrays Scheduling algorithm Computer architecture Programmable logic arrays Static Token Coarse-grained Reconfigurable Architecture Modulo Scheduling Routing Resource Graph Graph Homeomorphism |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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