NDLI: Optimization of Pattern Matching Circuits for Regular Expression on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Cheng-Hung Lin Chih-Tsun Huang Chang-Ping Jiang Shih-Chieh Chang
Copyright Year	1993
Abstract	Regular expressions are widely used in the network intrusion detection system (NIDS) to represent attack patterns. Previously, many hardware architectures have been proposed to accelerate regular expression matching using field-programmable gate array (FPGA) because FPGAs allow updating of new attack patterns. Because of the increasing number of attacks, we need to accommodate a large number of regular expressions on FPGAs. Although the minimization of logic equations has been studied intensively in the area of computer-aided design (CAD), the minimization of multiple regular expressions has been largely neglected. This paper presents a novel sharing architecture allowing our algorithm to extract and share common subregular expressions. Experimental results show that our sharing scheme significantly reduces the area of pattern matching circuits for regular expression.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1303
Ending Page	1310
Page Count	8
File Size	597345
File Format	PDF
ISSN	10638210
Volume Number	15
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pattern matching Circuits Field programmable gate arrays Intrusion detection Minimization Design automation Hardware Acceleration Logic design Equations pattern matching Finite automata field-programmable gate array (FPGA) intrusion detection
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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