NDLI: A Processor Allocation of DSP Applications Onto Heterogeneous Multiprocessor Architectures

Content Provider	IEEE Xplore Digital Library
Author	Itradat, A. Ahmad, M.O. Shatnawi, A.
Copyright Year	2007
Description	Author affiliation: Concordia Univ., Montreal (Itradat, A.; Ahmad, M.O.)
Abstract	In recent years a great deal of research has been conducted in the area of scheduling of DSP data flow graphs (DFG) onto multiprocessing systems. In this paper, a new processor allocation technique is proposed. Both heterogeneous and general-purpose functional units are used during the resource allocation process. The proposed technique provides the designer with more flexibility to explore the design space by using different types of processing modules for the same task. The proposed allocation technique leads to different multiprocessor architectures for a given rate-optimal schedule of a DSP data flow graph. A satisfactory function is used to infer the quality of the obtained architectures in terms of the area and utilization of each of them. The proposed algorithm is applied to a well-known benchmark problem of DSP filter. It is seen that moving from a fully-homogenous to a fully-heterogeneous multiprocessor architecture results in decreasing the area of the design. However, a hybrid multiprocessor architecture brings about a trade off between the area and the utilization.
Starting Page	944
Ending Page	947
File Size	256258
Page Count	4
File Format	PDF
ISBN	1424410207
ISSN	08407789
DOI	10.1109/CCECE.2007.241
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Hardware Resource management Computer architecture Flow graphs Processor scheduling Multiprocessing systems Space exploration Delay Costs
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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