NDLI: Systolic Array-Based Pipelining Design of CCK Demodulators

Content Provider	IEEE Xplore Digital Library
Author	Kok, A.Y.W. Law, K.L.E.
Copyright Year	2007
Description	Author affiliation: Ryerson Univ., Toronto (Kok, A.Y.W.; Law, K.L.E.)
Abstract	Complementary code keying (CCK) is one of the few channel coding techniques used in the widely deployed 802.11b wireless local area networks (WLANs). CCK is used for transmitting 5.5 and 11 Mbps data transfer rates. In this paper, we propose a design to improve the efficiency of CCK demodulation. The proposed systolic array architecture exploits and reuses the replicated butterfly structure of modified fast Walsh transform (MFWT). A typical MFWT CCK demodulator, consists of three stages, accepts all eight chips of the CCK codeword simultaneously, and outputs sixty-four values. Upon deploying the proposed systolic array design with its pipelining nature, instead of processing all eight chips of CCK in parallel during the first stage, every two chips can be processed immediately. At each stage, the results are moved instantly to the next stage upon multiplying the appropriate constants. This resulting systolic array architecture has many advantages over the conventional design. Firstly, a serial-to-parallel converter to convert serial incoming data to parallel blocks of eight chips is not required. This reduces hardware complexity. Secondly, every stage in the architecture is continuously processing data; whereas, in the conventional design, hardware in each stage is left idle after processing until inputs from the next eight chips block arrives. Thirdly, twenty-eight butterflies are needed in a conventional design, but, only thirteen butterflies are required due to hardware reuse in the proposed architecture.
Starting Page	70
Ending Page	73
File Size	300213
Page Count	4
File Format	PDF
ISBN	1424410207
ISSN	08407789
DOI	10.1109/CCECE.2007.25
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Systolic arrays Pipeline processing Demodulation Wireless LAN Spread spectrum communication Standards publication Hardware Code standards Physical layer Frequency
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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